公开(公告)号：US12112785B2

公开(公告)日：2024-10-08

申请号：US17732885

申请日：2022-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Angelo Visconti ,  Giorgio Servalli

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2273

Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

公开(公告)号：US12035536B2

公开(公告)日：2024-07-09

申请号：US17379012

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H10B51/50 ,  H01L25/065 ,  H01L29/786 ,  H10B53/30

CPC classification number: H10B51/50 ,  H01L25/0655 ,  H01L29/78642 ,  H10B53/30

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12001706B2

公开(公告)日：2024-06-04

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

公开(公告)号：US11764234B2

公开(公告)日：2023-09-19

申请号：US17680644

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/13 ,  H01L21/84 ,  H10B69/00 ,  H01L27/12 ,  H01L27/105

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/105 ,  H10B69/00

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US11706927B2

公开(公告)日：2023-07-18

申请号：US17189594

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H01L27/11514 ,  H10B51/20 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20 ,  H01L27/11597 ,  H01L27/11587 ,  H01L27/11504

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20

Abstract: Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

公开(公告)号：US20230010846A1

公开(公告)日：2023-01-12

申请号：US17371506

申请日：2021-07-09

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L27/088 ,  H01L21/8234

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11189330B2

公开(公告)日：2021-11-30

申请号：US17143800

申请日：2021-01-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

公开(公告)号：US20210264961A1

公开(公告)日：2021-08-26

申请号：US17196661

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Giorgio Servalli ,  Andrea Locatelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.

公开(公告)号：US20190252034A1

公开(公告)日：2019-08-15

申请号：US16392015

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50004 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297

Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

公开(公告)号：US20190081104A1

公开(公告)日：2019-03-14

申请号：US16185729

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L45/00

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.