公开(公告)号：US20230229560A1

公开(公告)日：2023-07-20

申请号：US17897037

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G06F11/14 ,  G06F12/06 ,  G06F11/10

CPC classification number: G06F11/1435 ,  G06F12/0646 ,  G06F11/1044 ,  G06F2212/1032 ,  G06F2201/805

Abstract: There are provided methods and systems for correcting an error from a memory. For example, there is provided a system for mitigating an error in a memory. The system can include a memory controller communicatively coupled to a host. The memory controller may be configured to receive information associated with a memory location. The information can indicate the error at the memory location. The controller may be configured to perform, upon receiving the information, certain operations. The operations can include copying data around the memory location, placing the copied data in a reserved area. And the operations can further include outputting, to a central controller, a set of physical addresses associated with the reserved area, wherein the central controller is configured to modify the set of physical address to conduct a data recovery off-line.

公开(公告)号：US11695072B2

公开(公告)日：2023-07-04

申请号：US17371506

申请日：2021-07-09

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/78391

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230014289A1

公开(公告)日：2023-01-19

申请号：US17379012

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H01L27/11595 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210304812A1

公开(公告)日：2021-09-30

申请号：US16834941

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097

Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

公开(公告)号：US11127744B2

公开(公告)日：2021-09-21

申请号：US16737171

申请日：2020-01-08

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H01L27/108 ,  H01L27/11504 ,  H01L27/11507 ,  G11C11/22

Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

公开(公告)号：US20210210491A1

公开(公告)日：2021-07-08

申请号：US16737171

申请日：2020-01-08

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H01L27/108 ,  H01L27/11504 ,  H01L27/11507 ,  G11C11/22

Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

公开(公告)号：US10658428B2

公开(公告)日：2020-05-19

申请号：US16185729

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L45/00

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

公开(公告)号：US10483463B2

公开(公告)日：2019-11-19

申请号：US16121433

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

公开(公告)号：US10410737B2

公开(公告)日：2019-09-10

申请号：US16392015

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

公开(公告)号：US10290456B2

公开(公告)日：2019-05-14

申请号：US15339699

申请日：2016-10-31

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Giorgio Servalli

IPC: H01H85/06 ,  H01H85/08 ,  G11C13/00 ,  H01H85/11 ,  H01H37/32

Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.