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    Memory Circuitry And Method Used In Forming Memory Circuitry
    21.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20230422483A1

    公开(公告)日：2023-12-28

    申请号：US18243298

    申请日：2023-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines. After forming the digitlines, the conductor material is patterned in another direction that is horizontally angled from the one direction to form conductor vias that are individually directly electrically coupled to the one source/drain region. A plurality of storage elements is formed that are individually directly electrically coupled to individual of the conductor vias. Other aspects, including structure independent of method, are disclosed.

    Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies
    23.
    发明授权
    Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies 有权

    公开(公告)号：US11239242B2

    公开(公告)日：2022-02-01

    申请号：US16880900

    申请日：2020-05-21

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

    IPC: H01L27/108

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

    PASSIVATION MATERIAL FOR A PILLAR ADJACENT A TRENCH
    25.
    发明申请
    PASSIVATION MATERIAL FOR A PILLAR ADJACENT A TRENCH 审中-公开

    公开(公告)号：US20200127080A1

    公开(公告)日：2020-04-23

    申请号：US16167016

    申请日：2018-10-22

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Mohd Kamran Akhtar

    IPC: H01L49/02 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L27/108 ,  H01L23/31 ,  H01L23/29

    Abstract: Systems, apparatuses, and methods related to passivation material for a pillar adjacent a trench are described. An example method includes forming a passivation material on a top region of a pillar adjacent a trench of a semiconductor device and removing a first portion of the passivation material to form, on a remaining second portion of the passivation material, a surface that is coplanar with an underlying sidewall of the pillar. The example method further includes removing a portion of a substrate material at a bottom region of the trench and removing the remaining second portion of the passivation material from the top region.

    METHODS OF FORMING SEMICONDUCTOR DEVICES, AND RELATED SEMICONDUCTOR DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    26.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES, AND RELATED SEMICONDUCTOR DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20200066729A1

    公开(公告)日：2020-02-27

    申请号：US16109215

    申请日：2018-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

    IPC: H01L27/108 ,  H01L21/764 ,  G11C11/408

    Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
    27.
    发明授权
    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines 有权

    公开(公告)号：US10134741B2

    公开(公告)日：2018-11-20

    申请号：US15652724

    申请日：2017-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

    IPC: H01L21/768 ,  H01L27/108

    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

    MEMORY DEVICE INCLUDING STRUCTURES IN MEMORY ARRAY REGION AND PERIPERAL CIRCUITRY REGION
    29.
    发明公开
    MEMORY DEVICE INCLUDING STRUCTURES IN MEMORY ARRAY REGION AND PERIPERAL CIRCUITRY REGION 审中-公开

    公开(公告)号：US20240064972A1

    公开(公告)日：2024-02-22

    申请号：US17892603

    申请日：2022-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee ,  Terrence B. Mcdaniel ,  Guangjun Yang ,  Vinay Nair

    IPC: H01L27/108

    CPC classification number: H01L27/10897 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    30.
    发明申请
    Memory Circuitry And Method Used In Forming Memory Circuitry 有权

    公开(公告)号：US20230005927A1

    公开(公告)日：2023-01-05

    申请号：US17364154

    申请日：2021-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang

    IPC: H01L27/108

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines. After forming the digitlines, the conductor material is patterned in another direction that is horizontally angled from the one direction to form conductor vias that are individually directly electrically coupled to the one source/drain region. A plurality of storage elements is formed that are individually directly electrically coupled to individual of the conductor vias. Other aspects, including structure independent of method, are disclosed.

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