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    SPLIT VIA STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGING
    21.
    发明公开
    SPLIT VIA STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGING 审中-公开

    公开(公告)号：US20240071869A1

    公开(公告)日：2024-02-29

    申请号：US17894102

    申请日：2022-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Hong Wan Ng ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/5283

    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

    Semiconductor devices with multiple substrates and die stacks
    23.
    发明授权
    Semiconductor devices with multiple substrates and die stacks 有权

    公开(公告)号：US11562987B2

    公开(公告)日：2023-01-24

    申请号：US17232333

    申请日：2021-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Chin Hui Chong ,  Hong Wan Ng ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

    IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

    Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

    THREE-DIMENSIONAL BONDING SCHEME AND ASSOCIATED SYSTEMS AND METHODS
    25.
    发明申请
    THREE-DIMENSIONAL BONDING SCHEME AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20250079405A1

    公开(公告)日：2025-03-06

    申请号：US18951102

    申请日：2024-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

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