公开(公告)号：US20240071980A1

公开(公告)日：2024-02-29

申请号：US17899550

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L23/49816 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/3512

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.

公开(公告)号：US20240057265A1

公开(公告)日：2024-02-15

申请号：US17885338

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Ling Pan

IPC: H05K3/34 ,  H05K1/02

CPC classification number: H05K3/3452 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/099

Abstract: Substrates having stress-releasing features, and associated systems and methods are disclosed herein. In some embodiments, the substrate includes a core layer, a metallization layer formed on an outer surface of the core layer, and a solder mask formed over the metallization layer and the outer surface. The metallization layer can include at least one bond pad and the solder mask can include a first opening exposing the bond pad. The first opening can be surrounded by a bonding region of the solder mask that thermally interfaces with the bond pad and/or any conductive structure bonded thereon. The solder mask can also include one or more second openings adjacent the first opening. Each of the second openings provides space for the solder mask to expand into to release stress due to thermal expansions of the bond pad, the solder mask, and/or the conductive structure during manufacturing and/or operation.

公开(公告)号：US20230378129A1

公开(公告)日：2023-11-23

申请号：US17750225

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

公开(公告)号：US20230378128A1

公开(公告)日：2023-11-23

申请号：US17750200

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

公开(公告)号：US11710722B2

公开(公告)日：2023-07-25

申请号：US17233129

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06572

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20230056648A1

公开(公告)日：2023-02-23

申请号：US17982397

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US12237301B2

公开(公告)日：2025-02-25

申请号：US17750225

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

公开(公告)号：US20240234390A1

公开(公告)日：2024-07-11

申请号：US18389613

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Dalson Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan

IPC: H01L25/16 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/48

Abstract: A microelectronic device package includes a stack of semiconductor dies positioned over a substrate. The microelectronic device package further includes an interposer structure coupled to the stack of semiconductor dies. The microelectronic device package further includes an electronic component directly coupled to the interposer structure and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate.

公开(公告)号：US20240072024A1

公开(公告)日：2024-02-29

申请号：US17897156

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/35121

Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.

公开(公告)号：US20240047423A1

公开(公告)日：2024-02-08

申请号：US17879660

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L21/304

CPC classification number: H01L25/0657 ,  H01L21/3043 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2924/10158 ,  H01L24/48

Abstract: A semiconductor device assembly is provided. The assembly includes an outer semiconductor device which has an active surface and a back surface. The back surface includes a cut that extends to a depth between the active surface and the back surface, and uncut regions on opposing sides of the cut. The assembly further includes an inner semiconductor device disposed within the cut of the outer semiconductor device.