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公开(公告)号：US20210191858A1
公开(公告)日：2021-06-24
申请号：US17196934
申请日：2021-03-09
Applicant: Micron Technology, Inc.
Inventor： Yun Li , Kishore Kumar Muchherla , Peter Feeley , Ashutosh Malshe , Daniel J. Hubbard , Christopher S. Hale , Kevin R. Brandt , Sampath K. Ratnam
IPC: G06F12/02 , G06F12/0891
Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.
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公开(公告)号：US11036631B2
公开(公告)日：2021-06-15
申请号：US15802551
申请日：2017-11-03
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G06F12/02 , G11C16/20 , G11C16/32 , G11C11/406 , G11C16/34 , G06F13/16 , G06F16/18 , G11C7/20 , G11C29/26 , G11C29/02 , G11C29/04
Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
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公开(公告)号：US10777292B2
公开(公告)日：2020-09-15
申请号：US16587283
申请日：2019-09-30
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G11C8/00 , G11C29/02 , G11C16/10 , G06F12/02 , G11C16/32 , G06F3/06 , G11C7/10 , G06F16/18 , G11C16/34 , G11C7/04 , G11C29/44
Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
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公开(公告)号：US10761980B2
公开(公告)日：2020-09-01
申请号：US16442792
申请日：2019-06-17
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G11C11/40 , G06F12/02 , G11C11/406 , G11C16/20 , G11C16/34 , G06F13/16 , G11C16/32 , G06F16/18 , G11C7/20 , G11C29/02 , G11C29/44
Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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25.发明授权公开(公告)号：US10685725B2
公开(公告)日：2020-06-16
申请号：US16514861
申请日：2019-07-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Peter Feeley , Kishore Kumar Muchherla , Renato C. Padilla , Shane Nowell
IPC: G11C11/34 , G11C16/34 , G11C7/04 , G11C7/22 , G11C11/56 , G11C16/04 , G11C16/26 , G06F13/16 , G11C7/10
Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
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Patent Agency Ranking
公开(公告)号：US10535415B2
公开(公告)日：2020-01-14
申请号：US15802597
申请日：2017-11-03
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
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公开(公告)号：US20190138442A1
公开(公告)日：2019-05-09
申请号：US15802551
申请日：2017-11-03
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
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公开(公告)号：US20180286482A1
公开(公告)日：2018-10-04
申请号：US16001387
申请日：2018-06-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Koji Sakui , Peter Feeley
CPC classification number: G11C16/0408 , G11C16/0433 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.
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公开(公告)号：US20180196705A1
公开(公告)日：2018-07-12
申请号：US15911490
申请日：2018-03-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael G. Miller , Ashutosh Malshe , Violante Moschiano , Peter Feeley , Gary F. Besinga , Sampath K. Ratnam , Walter Di-Francesco , Renato C. Padilla, JR. , Yun Li , Kishore Kumar Muchherla
CPC classification number: G06F11/073 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/0751 , G06F11/0772 , G06F11/079
Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
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公开(公告)号：US09318220B2
公开(公告)日：2016-04-19
申请号：US14182032
申请日：2014-02-17
Applicant: Micron Technology, Inc.
Inventor： Zhenlei Shen , William H. Radke , Peter Feeley
CPC classification number: G06F11/1068 , G06F11/1004 , G06F11/1048 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C29/04 , G11C29/52
Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.
Abstract translation: 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。
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