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公开(公告)号：US20250013370A1
公开(公告)日：2025-01-09
申请号：US18890173
申请日：2024-09-19
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Ching-Huang Lu , Devin Batutis
Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.
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公开(公告)号：US20240412803A1
公开(公告)日：2024-12-12
申请号：US18676267
申请日：2024-05-28
Applicant: Micron Technology, Inc.
Inventor： Qun Su , Pitamber Shukla
Abstract: Exemplary methods, apparatuses, and systems write data to a first wordline of a partially programmed block of memory. A second wordline of the block is determined to fail to satisfy a first margin threshold by comparing a first voltage threshold of the second wordline to a reference voltage. In response to the second wordline failing to satisfy the first margin threshold, a second margin test is applied to the block. In response to determining the block passed the second margin test, data is written in a subsequent write operation to the block using an adjusted trim setting.
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公开(公告)号：US20240339172A1
公开(公告)日：2024-10-10
申请号：US18624720
申请日：2024-04-02
Applicant: Micron Technology, Inc.
Inventor： Yugang Yu , Chun Sum Yeung , Pitamber Shukla
CPC classification number: G11C29/52 , G11C29/022 , G11C29/028
Abstract: Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.
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公开(公告)号：US20240152279A1
公开(公告)日：2024-05-09
申请号：US17982750
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Pitamber Shukla , Akira Goda
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: An apparatus can include a touch-up component. The touch-up component can detect a first charge parameter for a portion of memory of a memory system. The touch-up component can, subsequent to detecting the first charge parameter a particular time interval, detect a second charge parameter for the portion of memory. The touch-up component can determine a charge parameter change per time interval based on the first charge parameter, the second charge parameter, and the particular time interval. The touch-up component can perform a touch-up operation on the portion of memory at a particular time point based on the charge parameter change per time interval.
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25.发明授权公开(公告)号：US11972114B2
公开(公告)日：2024-04-30
申请号：US17867204
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Sandeep Reddy Kadasani , Pitamber Shukla , Scott Anthony Stoller , Niccolo' Righetti
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0688
Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.
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Patent Agency Ranking
26.发明公开公开(公告)号：US20240071528A1
公开(公告)日：2024-02-29
申请号：US17897441
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Robert W. Mason , Scott Anthony Stoller , Pitamber Shukla , Ekamdeep Singh
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/3495
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.
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公开(公告)号：US20230418475A1
公开(公告)日：2023-12-28
申请号：US17848061
申请日：2022-06-23
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Ching-Huang Lu , Devin Batutis
CPC classification number: G06F3/0619 , G06F3/0608 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/076 , G06F11/002
Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.
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公开(公告)号：US20230333762A1
公开(公告)日：2023-10-19
申请号：US17721555
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Robert Mason , Pitamber Shukla , Scott Anthony Stoller , Stuart A. Bell , Dennis J. Borgonos
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: A failure of a block among a set of blocks of a memory device of a memory subsystem is detected. Based on detecting the failure of the block, the block is evaluated for reuse. The block is designated for reuse based on a result of the evaluating of the block. The block is allocated to a task based on the block being designated for reuse.
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公开(公告)号：US11556410B2
公开(公告)日：2023-01-17
申请号：US17205545
申请日：2021-03-18
Applicant: Micron Technology, Inc.
Inventor： Scott Anthony Stoller , Pitamber Shukla , Anita Marguerite Ekren
Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.
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公开(公告)号：US11468949B2
公开(公告)日：2022-10-11
申请号：US17200607
申请日：2021-03-12
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Giuseppina Puzzilli , Niccolo′ Righetti , Scott A. Stoller , Priya Venkataraman
Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.
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