公开(公告)号：US20240303187A1

公开(公告)日：2024-09-12

申请号：US18591368

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Ryan Hrinya ,  Fulvio Rori ,  Scott A. Stoller ,  Tyler Betz

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.

公开(公告)号：US11721404B2

公开(公告)日：2023-08-08

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/349 ,  G11C16/12 ,  G11C2211/5641

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11709616B2

公开(公告)日：2023-07-25

申请号：US17890885

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo′ Righetti

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0625 ,  G06F3/0679

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20220391125A1

公开(公告)日：2022-12-08

申请号：US17890885

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US12027227B2

公开(公告)日：2024-07-02

申请号：US17426963

申请日：2020-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

公开(公告)号：US11468949B2

公开(公告)日：2022-10-11

申请号：US17200607

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Giuseppina Puzzilli ,  Niccolo′ Righetti ,  Scott A. Stoller ,  Priya Venkataraman

IPC: G11C11/00 ,  G11C16/10 ,  G11C7/04 ,  G11C16/32 ,  G11C16/26

Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

公开(公告)号：US11461035B2

公开(公告)日：2022-10-04

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20220199163A1

公开(公告)日：2022-06-23

申请号：US17127358

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Priya Venkataraman ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

公开(公告)号：US20220013182A1

公开(公告)日：2022-01-13

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US20180293001A1

公开(公告)日：2018-10-11

申请号：US15479356

申请日：2017-04-05

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G11C16/00

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.