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    Semiconductor integrated circuit device
    21.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07944256B2

    公开(公告)日：2011-05-17

    申请号：US12010597

    申请日：2008-01-28

    Applicant: Noboru Masuda

    Inventor： Noboru Masuda

    IPC: H03L7/06

    CPC classification number: H03D13/004 ,  H03L7/0895 ,  H03L7/0995 ,  H03L7/113

    Abstract: High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely.

    Abstract translation: 实现了由PLL电路等表示的各种反馈系统的高精度。 例如，在PLL电路中的电荷泵电路中，在电源电压和输出节点之间设置串联连接的三级PMOS晶体管的第一至第三PMOS晶体管，以及串联连接的第一至第三NMOS晶体管 在地电压和输出节点之间提供三级。 并且，当通过第一脉冲信号在电源电压或接地电压和输出节点之间建立导电性时，第二PMOS晶体管和第二NMOS晶体管被驱动为导通，并且当第一PMOS晶体管和第三NMOS晶体管被驱动为截止时 电导率被第二脉冲信号关闭。 因此，可以通过第一脉冲信号的一个边缘和第二脉冲信号的一个边缘之间的时间差来设置导通时间，因此可以设置短的导通时间，结果是电荷泵电路的充电量 可以精确控制。

    Semiconductor integrated circuit device
    22.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20080218217A1

    公开(公告)日：2008-09-11

    申请号：US12010597

    申请日：2008-01-28

    Applicant: Noboru Masuda

    Inventor： Noboru Masuda

    IPC: H03L7/085 ,  H03D13/00 ,  H03L7/08 ,  G05F1/10

    CPC classification number: H03D13/004 ,  H03L7/0895 ,  H03L7/0995 ,  H03L7/113

    Abstract: High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely.

    Abstract translation: 实现了由PLL电路等表示的各种反馈系统的高精度。 例如，在PLL电路中的电荷泵电路中，在电源电压和输出节点之间设置串联连接的三级PMOS晶体管的第一至第三PMOS晶体管，以及串联连接的第一至第三NMOS晶体管 在地电压和输出节点之间提供三级。 并且，当通过第一脉冲信号在电源电压或接地电压和输出节点之间建立导电性时，第二PMOS晶体管和第二NMOS晶体管被驱动为导通，并且当第一PMOS晶体管和第三NMOS晶体管被驱动为截止时 电导率被第二脉冲信号关闭。 因此，可以通过第一脉冲信号的一个边缘和第二脉冲信号的一个边缘之间的时间差来设置导通时间，因此可以设置短的导通时间，结果是电荷泵电路的充电量 可以精确控制。

    Intermittent coating apparatus and intermittent coating method
    23.
    发明授权
    Intermittent coating apparatus and intermittent coating method 失效

    公开(公告)号：US07105203B1

    公开(公告)日：2006-09-12

    申请号：US09498749

    申请日：2000-02-07

    Applicant: Noboru Masuda ,  Masaru Watanabe

    Inventor： Noboru Masuda ,  Masaru Watanabe

    IPC: B05D5/00

    CPC classification number: B05C11/1047 ,  B05C5/0258 ,  B05C11/10 ,  B05D1/26 ,  B05D5/00 ,  B05D2252/02

    Abstract: The intermittent coating apparatus which includes a nozzle 1 which applies a paint 6 to a base material, a feeding side two-way valve 10 which repeats feeding of the paint 6 to the nozzle 1 and stop of the feeding, a return side two-way valve which 11 repeats discharge of the paint 6 to a return side and stop of the discharge, a paint flow path 12, means to feed the paint 6 into the flow path 12, and paint returning means 5 which repeats suction and return of the paint 6 out of and into the nozzle 1, and is characterized in that switching of the feeding side two-way valve 10 is carried out earlier than that of the return side two-way valve 11 within a range not shorter than 5 msec and not longer than 100 msec at least at a coating start time.

    Dynamic logic circuit and integrated circuit device using the logic circuit
    25.
    发明授权
    Dynamic logic circuit and integrated circuit device using the logic circuit 失效
    动态逻辑电路和集成电路器件采用逻辑电路

    公开(公告)号：US06278296B1

    公开(公告)日：2001-08-21

    申请号：US09369199

    申请日：1999-08-06

    Applicant: Noboru Masuda ,  Michitaka Yamamoto

    Inventor： Noboru Masuda ,  Michitaka Yamamoto

    IPC: H03K19096

    CPC classification number: H03K19/0963

    Abstract: In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced. Therefore, a signal delay time is reduced.

    Abstract translation: 在动态逻辑电路中，输入信号的从低到高跃迁与输出信号的低电平到高转换之间的信号延迟时间减小，直流电流减小，预充电所需的时间为 减少 在动态逻辑电路中，P沟道型MOS晶体管（PMOS）的源电极与高压电位Vdd侧的电源连接。 其栅电极接收时钟信号Cs。 逻辑部分包括连接在PMOS的漏电极和低电压电位Vss侧的电源之间的N沟道型MOS晶体管（NMOS）。 在与NMOS中的最接近Vss的NMOS连接的输入信号和Vss之间提供NMOS。 时钟信号Cs的反向信号与NMOS的栅电极连接。 在预充电时强制输入信号变为低电平，从而减小通电流，并减少预充电所需的时间。 因此，信号延迟时间减少。

    Variable delay circuit and clock signal supply unit using the same
    27.
    发明授权
    Variable delay circuit and clock signal supply unit using the same 失效
    可变延迟电路和时钟信号供给单元使用相同

    公开(公告)号：US5497263A

    公开(公告)日：1996-03-05

    申请号：US117525

    申请日：1993-09-07

    Applicant: Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

    Inventor： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

    IPC: G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

    CPC classification number: H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

    Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

    Abstract translation: 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。

    Infrared ray detector
    30.
    发明授权
    Infrared ray detector 失效
    红外线探测器

    公开(公告)号：US4745284A

    公开(公告)日：1988-05-17

    申请号：US866641

    申请日：1986-05-27

    Applicant: Noboru Masuda ,  Kenji Tomaki ,  Tetsuo Oosawa ,  Michihiro Murata

    Inventor： Noboru Masuda ,  Kenji Tomaki ,  Tetsuo Oosawa ,  Michihiro Murata

    IPC: G08B13/19 ,  G01J5/08

    CPC classification number: G08B13/19 ,  Y10S250/01

    Abstract: A pyroelectric infrared ray detector of the so-called dual structure for detecting an intruder or the like through differential output of two pyroelectric infrared ray detecting elements connected in parallel or series to each other. The infrared ray detector comprises a pair of pyroelectric infrared ray detecting elements having substantially identically directed light receiving surfaces and electrically connected to each other and a shield member arranged in front of the said light receiving surfaces to partially shield the infrared ray detecting elements against incidence of infrared light. The shield member is arranged in a plane extending between the infrared ray detecting elements to separate the same on both sides thereof.

    Abstract translation: 用于通过两个并联或串联连接的两个热释电红外线检测元件的差分输出来检测入侵者等的所谓的双重结构的热释电红外线检测器。 红外线检测器包括一对热电红外线检测元件，其具有基本相同的光接收表面并彼此电连接，并且屏蔽构件布置在所述光接收表面的前面，以部分地屏蔽红外线检测元件以防止 红外灯。 屏蔽构件布置在延伸在红外线检测元件之间的平面中，以在其两侧分离。

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