公开(公告)号：US20120047710A1

公开(公告)日：2012-03-01

申请号：US13190665

申请日：2011-07-26

Applicant: Yukihiro HIRAMOTO ,  Noboru Masuda

Inventor： Yukihiro HIRAMOTO ,  Noboru Masuda

IPC: B23P17/00 ,  B23P13/00

CPC classification number: B23P13/02 ,  B23P15/00 ,  Y10T29/49025 ,  Y10T29/49636 ,  Y10T29/49639 ,  Y10T29/49696 ,  Y10T29/49885 ,  Y10T29/49996

Abstract: A manufacturing method of a rotating device includes a first machining process of machining a bearing hole while supplying a first cutting lubricant to a base member, a second machining process continuous from the first machining process, the second machining process being of machining a tap hole while supplying a second cutting lubricant to the base member, a blowing process of blowing at least either one of the bearing hole and the tap hole with a fluid in order to eliminate a machining residue, the blowing process including an air spraying process and a liquid spraying process, a cleaning process of cleaning the base member, and an assembling process of assembling the base member with the bearing unit and the rotating body.

Abstract translation: 旋转装置的制造方法包括在向基材供给第一切削润滑剂的同时加工轴承孔的第一加工工序，从第一加工工序连续的第二加工工序，第二加工工序是加工出孔， 向所述基座部件供给第二切削润滑剂，利用流体吹送所述轴承孔和所述排出孔中的至少一个的吹塑工序，以消除机械残留物，所述吹塑法包括空气喷涂法和喷液法 过程，清洁基座构件的清洁过程以及组装基座与轴承单元和旋转体的组装过程。

公开(公告)号：US20090160508A1

公开(公告)日：2009-06-25

申请号：US12068513

申请日：2008-02-07

Applicant: Noboru Masuda

Inventor： Noboru Masuda

IPC: H03L7/087

CPC classification number: H03L7/113 ,  H03K19/018528 ,  H03L7/0898 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/18

Abstract: Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced.

Abstract translation: 混合控制型PLL电路处于稳定状态的相位抖动减小。 确定混合控制型PLL电路中的相位比较电路的输出频率是否变化的稳态检测电路是否被提供，如果相位比较电路的输出对于 同时，如果相位比较电路的输出频繁变化，则确定已经达到稳定状态，并且基于确定结果，通过数字控制信号控制压控振荡器电路的振荡频率的控制宽度为 改变或（和）改变模拟控制信号的频率被改变。 由此，可以在达到稳定状态之前通过数字控制信号的振荡频率的控制宽度降低，而不会在达到稳定状态之前损害收敛。 因此，能够降低稳定状态下的相位抖动。

公开(公告)号：US06316961B2

公开(公告)日：2001-11-13

申请号：US09725812

申请日：2000-11-30

Applicant: Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

Inventor： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

IPC: H03K19096

CPC classification number: H03K19/0963 ,  H03K19/1738

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

公开(公告)号：US5576997A

公开(公告)日：1996-11-19

申请号：US309418

申请日：1994-09-20

Applicant: Noboru Masuda ,  Kazunori Nakajima ,  Hideo Maejima

Inventor： Noboru Masuda ,  Kazunori Nakajima ,  Hideo Maejima

IPC: G06F12/00 ,  G11C5/06 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/1048 ,  G11C5/063

Abstract: A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.

Abstract translation: 具有逻辑LSI，多个存储器LSI的数据处理系统和消除从存储器LSI读出的数据到达逻辑LSI的时间的延迟的电路。 电路包括用于延迟从存储器LSI读出的数据信号的可变延迟电路。 控制电路开始监视从个别存储器LSI读出的数据到达将数据输出到逻辑LSI的触发器的时间。 可变延迟电路中的延迟时间由各个存储器LSI的控制电路控制，使得从存储器LSI读出的数据达到逻辑LSI的时间可以与预定的标准时间一致。 因此，来自各个存储器LSI的读取数据被同时到达触发器。

公开(公告)号：US5231359A

公开(公告)日：1993-07-27

申请号：US526247

申请日：1990-05-18

Applicant: Noboru Masuda ,  Tetsuo Ohsawa ,  Takashi Sugimura

Inventor： Noboru Masuda ,  Tetsuo Ohsawa ,  Takashi Sugimura

IPC: G01V3/08 ,  G11B9/06

CPC classification number: G01V3/088 ,  G11B9/06

Abstract: A ceramic resonance type electrostatic sensor apparatus with an oscillator at a fixed frequency including a first ceramic resonator which has a fixed resonance frequency, a detecting unit for detecting a capacitance between the detecting unit and an object to be detected, a resonating circuit including a second ceramic resonator and having a resonance point which varies with the small change in capacitance detected by the detecting unit, a high impedance circuit connected between the oscillator and the resonating circuit, and a high impedance circuit connected between the resonating circuit and the detecting circuit.

公开(公告)号：US5150068A

公开(公告)日：1992-09-22

申请号：US391782

申请日：1989-08-09

Applicant: Seiichi Kawashima ,  Noboru Masuda ,  Shuichi Ishii ,  Bunichi Fujita

Inventor： Seiichi Kawashima ,  Noboru Masuda ,  Shuichi Ishii ,  Bunichi Fujita

IPC: G06F1/10 ,  H03K5/13 ,  H03K5/15

CPC classification number: H03K5/13 ,  G06F1/10 ,  H03K5/15066 ,  H03K5/1508

Abstract: The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal have a period longer than that of the clock signal. The clock signal at a clock signal destination end is frequency divided in synchronism with the synchronizing signal to provide a sample to be compared with the reference signal. The resultant frequency-divided signal is compared with the reference signal in phase. A delay control is made for the clock signal in accordance with the result of the comparison to adjust the phase of the clock signal at the signal destinations.

Abstract translation: 本发明提供了一种时钟信号提供方法和系统。 在时钟信号发生源端产生参考信号和同步信号以及时钟信号。 参考信号和同步信号都具有比时钟信号长的周期。 时钟信号目的地端的时钟信号与同步信号同步地分频，以提供与参考信号进行比较的采样。 将得到的分频信号与参考信号同相进行比较。 根据比较结果对时钟信号进行延迟控制，以调整信号目的地的时钟信号的相位。

公开(公告)号：US5071329A

公开(公告)日：1991-12-10

申请号：US483727

申请日：1990-02-23

Applicant: Fumiaki Sano ,  Norihide Kobayashi ,  Hiroshi Ogawa ,  Noboru Masuda

Inventor： Fumiaki Sano ,  Norihide Kobayashi ,  Hiroshi Ogawa ,  Noboru Masuda

IPC: F01C1/02 ,  F01C17/06 ,  F04C18/02 ,  F04C23/00 ,  F16D3/04

CPC classification number: F01C17/066 ,  F04C18/0215 ,  F16D3/04 ,  F04C23/008 ,  Y10S464/903

Abstract: A scroll type fluid transferring machine comprises a stationary scroll having a wrap member, a movable scroll having a wrap member combined with the stationary scroll, a driving means for causing the movement of revolution of the movable scroll along a circular orbit so as to make the movable scroll line-contact with the stationary scroll whereby a closed space is produced between the stationary and movable scrolls, and an Oldham ring for maintaining the stationary and movable scrolls at predetermined positions while the movement of rotation of the both scrolls are prevented, wherein the Oldham ring is formed by injection-molding at least one thermoplastic resinous material selected from the group consisting of polyphenylene sulfide, polyetheretherketone, polyetherketone, wholly aromatic polyester, polysulfone, polyarylsulfone, polyethersulfone, polyetherimide, polyoxybenzyliden polyketonsulfide, polythioethersulfone and polyarylate.

Abstract translation: 一种涡旋式流体输送机，包括具有卷绕部件的固定涡旋件，具有与固定涡旋盘结合的涡卷部件的动涡旋盘，用于使动涡旋盘沿圆形轨道旋转的驱动装置， 活动涡旋线与固定涡旋件接触，从而在固定涡旋件和可动涡旋件之间产生闭合空间，以及用于在预定位置保持固定和可动涡旋件的杜尔汉姆环，同时防止两个涡旋件的旋转运动，其中 至少一种选自聚苯硫醚，聚醚醚酮，聚醚酮，全芳香族聚酯，聚砜，聚芳基砜，聚醚砜，聚醚酰亚胺，聚氧化亚苄基聚硫醚，聚硫醚砜，聚芳酯等的热塑性树脂材料注塑成型。

公开(公告)号：US5043596A

公开(公告)日：1991-08-27

申请号：US395958

申请日：1989-08-18

Applicant: Noboru Masuda ,  Hiroyuki Itoh ,  Bunichi Fujita ,  Seiichi Kawashima ,  Shuichi Ishii

Inventor： Noboru Masuda ,  Hiroyuki Itoh ,  Bunichi Fujita ,  Seiichi Kawashima ,  Shuichi Ishii

IPC: G06F1/06 ,  G06F1/10

CPC classification number: G06F1/06 ,  G06F1/10

Abstract: The present invention relates to a clock signal supplying device provided with an automatic phase regulating function for preventing errors in the phase regulation due to noise. In the device according to the present invention, there is disposed a reference signal serving as a phase reference, and transmission lines for clock signals and a transmission line for the reference signal are disposed from a clock signal supplying source to devices which are destinations of the distribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device, which is the destination of distribution of the clock signal, there is disposed a variable delay circuit for regulation of the phase of the clock signal and a phase comparing circuit for comparing the output of the variable delay circuit with the phase of the reference signal to output the result of the comparison. In the device according to the present invention, a noise filter is provided which detects phase regulation errors to effect correct phase regulation. Furthermore, the phase regulation is effected while avoiding a period of time wherein noise is apt to be produced.

公开(公告)号：US4954866A

公开(公告)日：1990-09-04

申请号：US247250

申请日：1988-09-21

Applicant: Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

Inventor： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

IPC: H01L27/06 ,  H01L27/105 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

Abstract: A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

Abstract translation: 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

公开(公告)号：US4723082A

公开(公告)日：1988-02-02

申请号：US884896

申请日：1986-07-14

Applicant: Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

Inventor： Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

IPC: H01L27/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H03K19/0185 ,  H03K19/017 ,  H03K19/094

CPC classification number: H03K19/018521 ,  H03K19/018557

Abstract: A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

Abstract translation: 叠层多层电路由具有每个内部电路并且彼此层叠的晶片组成。 在用于通过静电电容器在晶片之间传递信号的叠层多层电路中使用的信号传输电路具有足够高的输入电阻的接收电路，用于从形成静电电容器的电容电极接收信号，以及用于钳位 信号的电平基本上在接收电路的输入幅度内。 信号传送电路允许不通过触发器等执行信号传送，并且因此以高速执行信号传送。