公开(公告)号：US20230387954A1

公开(公告)日：2023-11-30

申请号：US18315336

申请日：2023-05-10

Applicant: QUALCOMM Incorporated

Inventor： Erwin SPITS ,  Adrianus VAN BEZOOIJEN ,  Francesco GATTA ,  Ryan Scott Castro SPRING

IPC: H04B1/16 ,  H04B1/00

CPC classification number: H04B1/1615 ,  H04B1/006

Abstract: An antenna detuning method includes: time domain duplexing signal transmission and signal reception by a first antenna of a wireless communication device; providing one or more first indications of time domain duplexing and one or more second indications of signal transmission to a semi-autonomous hardware controller of the wireless communication device; and responding, at the semi-autonomous hardware controller of the wireless communication device, to the one or more first indications of time domain duplexing and the one or more second indications of signal transmission by coupling a second antenna of the wireless communication device to receive circuitry during signal reception by the first antenna and to a termination during signal transmission by the first antenna.

公开(公告)号：US20220247445A1

公开(公告)日：2022-08-04

申请号：US17156352

申请日：2021-01-22

Applicant: QUALCOMM Incorporated

Inventor： Matthew SIENKO ,  Peter SHAH ,  Francesco GATTA

IPC: H04B1/40 ,  H04L27/227

Abstract: A switching mixer array is disclosed for the mixing of a digital LO signal with an analog input signal. Each switching mixer in the array is configured to assume either a first switching state or second switching state responsive to a respective bit of the digital LO signal.

公开(公告)号：US20210408989A1

公开(公告)日：2021-12-30

申请号：US17318959

申请日：2021-05-12

Applicant: QUALCOMM Incorporated

Inventor： Ahmed ABBAS MOHAMED HELMY ,  Mehran BAKHSHIANI ,  Francesco GATTA ,  Hasnain LAKDAWALA ,  Rahul KARMAKER ,  Shankar GUHADOS

IPC: H03F3/45 ,  H03G3/30

Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

公开(公告)号：US20250132736A1

公开(公告)日：2025-04-24

申请号：US18829889

申请日：2024-09-10

Applicant: QUALCOMM Incorporated

Inventor： Alaaeldien Mohamed Abdelrazek MEDRA ,  Xingyi HUA ,  Naushad DHAMANI ,  Francesco GATTA

IPC: H03F3/19 ,  H04B1/16

Abstract: Aspects of the present disclosure relate to a receiver including an amplifier circuit. The amplifier circuit includes a common-source amplifier having an input and an output, and a common-gate amplifier having an input and an output, wherein the input of the common-gate amplifier is coupled to the output of the common-source amplifier. The receiver also includes a first receive chain coupled to the output of the common-gate amplifier, and a second receive chain coupled to the output of the common-source amplifier.

公开(公告)号：US20240248870A1

公开(公告)日：2024-07-25

申请号：US18157000

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Umesh SRIKANTIAH ,  Lalan Jee MISHRA ,  Francesco GATTA ,  Richard Dominic WIETFELDT

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

公开(公告)号：US20230097399A1

公开(公告)日：2023-03-30

申请号：US17448750

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Ahmed ABBAS MOHAMED HELMY ,  Francesco GATTA ,  Balasubramanian RAMACHANDRAN ,  Abhishek Ananthrao KULKARNI ,  Prakash THOPPAY EGAMBARAM ,  Hasnain LAKDAWALA ,  Aleksandar Miodrag TASIC ,  Jang Joon LEE ,  Kyle David HOLLAND

IPC: H04B1/40 ,  H04B1/10

Abstract: Certain aspects of the present disclosure generally relate to techniques and apparatus for operating a wireless receiver of the apparatus in a high linearity mode. An example method includes operating the apparatus in a first mode with transmission of a plurality of transmit signals. The method also includes attenuating a received signal via an attenuator while operating the apparatus in the first mode. The method further includes amplifying the attenuated signal with an amplifier while operating the apparatus in the first mode. For certain aspects, the method further involves operating the apparatus in a second mode, bypassing the attenuator while operating the apparatus in the second mode, and amplifying the received signal with the amplifier while operating the apparatus in the second mode.

公开(公告)号：US20230095161A1

公开(公告)日：2023-03-30

申请号：US17485016

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hasnain LAKDAWALA ,  Ahmed ABBAS MOHAMED HELMY ,  Francesco GATTA ,  Balasubramanian RAMACHANDRAN ,  Ketan HUMNABADKAR ,  Andrea FENAROLI

IPC: H04B1/403 ,  H04W72/04

Abstract: Techniques and apparatus are described for reducing power consumption when performing wireless communications by dynamically changing the frequency of a local oscillator signal for a radio frequency (RF) downconversion circuit, based on signal conditions. An example method includes receiving an RF signal and downconverting the RF signal using an oscillating signal with a first frequency at a first time. The method also includes switching to downconverting the RF signal using the oscillating signal with a second frequency, based on a property associated with the RF signal at a second time. The second frequency is a subharmonic of the first frequency.

公开(公告)号：US20220190950A1

公开(公告)日：2022-06-16

申请号：US17124368

申请日：2020-12-16

Applicant: QUALCOMM Incorporated

Inventor： Lai Kan LEUNG ,  Aleksandar Miodrag TASIC ,  Francesco GATTA ,  Chiewcharn NARATHONG ,  Kyle David HOLLAND

IPC: H04K3/00 ,  H03F3/19 ,  H03M1/12

Abstract: The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.

公开(公告)号：US20220094310A1

公开(公告)日：2022-03-24

申请号：US17478746

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Alaaeldien Mohamed Abdelrazek MEDRA ,  Xingyi HUA ,  Naushad DHAMANI ,  Francesco GATTA

IPC: H03F3/19 ,  H04B1/16

Abstract: Aspects of the present disclosure relate to a receiver including an amplifier circuit. The amplifier circuit includes a common-source amplifier having an input and an output, and a common-gate amplifier having an input and an output, wherein the input of the common-gate amplifier is coupled to the output of the common-source amplifier. The receiver also includes a first receive chain coupled to the output of the common-gate amplifier, and a second receive chain coupled to the output of the common-source amplifier.

公开(公告)号：US20170310458A1

公开(公告)日：2017-10-26

申请号：US15269320

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Giovanni MARUCCI ,  Tsai-Pi HUNG ,  Francesco GATTA ,  Bo SUN

IPC: H04L7/033 ,  H04W72/04 ,  H04B1/40

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.