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公开(公告)号:US20240281401A1
公开(公告)日:2024-08-22
申请号:US18171264
申请日:2023-02-17
Applicant: QUALCOMM Incorporated
Inventor: Lalan Jee MISHRA , Richard Dominic WIETFELDT , Umesh SRIKANTIAH , Francesco GATTA , Christopher Kong Yee CHUN
CPC classification number: G06F13/4282 , G06F13/4022 , G06F2213/0018
Abstract: A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.
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公开(公告)号:US20240137788A1
公开(公告)日:2024-04-25
申请号:US18047995
申请日:2022-10-18
Applicant: QUALCOMM Incorporated
Inventor: Yongle WU , Francesco GATTA , Alexei Yurievitch GOROKHOV , Hari SANKAR , Christos KOMNINAKIS , Michael Lee MCCLOUD
IPC: H04W24/08
CPC classification number: H04W24/08
Abstract: A UE may attempt, based on a first mode, to identify a first opportunity within a preconfigured time period for a measurement associated with at least one SCC when the at least one SCC is deactivated at the UE and the measurement associated with the at least one SCC is due based on a scheduling. Based on the first mode, a radio of the UE may not be tuned to the at least one SCC when the at least one SCC is deactivated at the UE and no measurement associated with the at least one SCC is being performed at the UE. The UE may perform, if the first opportunity is identified within the preconfigured time period, the measurement associated with the at least one SCC at the identified first opportunity.
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公开(公告)号:US20240097801A1
公开(公告)日:2024-03-21
申请号:US17950093
申请日:2022-09-21
Applicant: QUALCOMM Incorporated
Inventor: Erwin SPITS , Francesco GATTA , Adrianus VAN BEZOOIJEN , Leon METREAUD , Hakan INANOGLU
CPC classification number: H04B17/0085 , H04B17/12 , H04B17/13 , H04B17/21
Abstract: A wireless communication device is provided with an in-device capability of characterizing the coupling between a pair of antennas. The wireless communication device determines the coupling through an operating gain measurement and through calibration gain measurements obtained through test ports.
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4.
公开(公告)号:US20210409041A1
公开(公告)日:2021-12-30
申请号:US17318968
申请日:2021-05-12
Applicant: QUALCOMM Incorporated
Inventor: Ahmed ABBAS MOHAMED HELMY , Mehran BAKHSHIANI , Francesco GATTA
Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.
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公开(公告)号:US20210367623A1
公开(公告)日:2021-11-25
申请号:US16882313
申请日:2020-05-22
Applicant: QUALCOMM Incorporated
Inventor: Rahul KARMAKER , Francesco GATTA
Abstract: According to certain aspects, a chip includes a first port, a first amplifier, and a first input path coupling the first port to an input of the first amplifier. The chip also includes a second port, a second amplifier, and a second input path coupling the second port to an input of the second amplifier. The chip further includes a switchable path coupled between the first input path and the second input path.
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公开(公告)号:US20240241853A1
公开(公告)日:2024-07-18
申请号:US18155499
申请日:2023-01-17
Applicant: QUALCOMM Incorporated
Inventor: Lalan Jee MISHRA , Umesh SRIKANTIAH , Francesco GATTA , Richard Dominic WIETFELDT
CPC classification number: G06F13/4295 , G06F13/24
Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.
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公开(公告)号:US20240097736A1
公开(公告)日:2024-03-21
申请号:US17949174
申请日:2022-09-20
Applicant: QUALCOMM Incorporated
Inventor: Adrianus VAN BEZOOIJEN , Francesco GATTA , Erwin SPITS
CPC classification number: H04B1/50 , H04B1/04 , H04B1/1607 , H04B2001/0408
Abstract: A user equipment (UE) is provided that detunes a receive antenna while a transmit antenna transmits. To determine the detuning, the UE first transmits a signal through the transmit antenna while the receive antenna is sequentially coupled through known loads. At each load, the UE determines an input reflection coefficient for a transmit path to the transmit antenna. Based upon the known loads and the corresponding input reflection coefficients, the UE determines a load to couple to the receive antenna to perform the detuning.
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公开(公告)号:US20240048162A1
公开(公告)日:2024-02-08
申请号:US18363321
申请日:2023-08-01
Applicant: QUALCOMM Incorporated
Inventor: Francesco GATTA , Balasubramanian RAMACHANDRAN , Abhishek Ananthrao KULKARNI , Soon-Seng LAU
CPC classification number: H04B1/0064 , H04B1/0475 , H04B1/18
Abstract: A system for wireless communications includes a first radio frequency front-end (RFFE) circuit coupled to a first antenna and a second RFFE coupled to a second antenna. The first RFFE circuit includes a first filter having a first passband spanning a first frequency band, a first low-noise amplifier (LNA) coupled to the first filter, and a bypass circuit configured to bypass the first filter, the bypass circuit including an attenuator. The first RFFE also includes a first switching circuit configured to couple the first antenna to the first filter or the bypass circuit. The second RFFE circuit includes a power amplifier, and a second filter coupled between the power amplifier and the second antenna, the second filter having a second passband spanning a second frequency band different than the first frequency band.
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9.
公开(公告)号:US20240012778A1
公开(公告)日:2024-01-11
申请号:US17861886
申请日:2022-07-11
Applicant: QUALCOMM Incorporated
Inventor: Lalan Jee MISHRA , Umesh SRIKANTIAH , Francesco GATTA , Muhlis Kenan OZEL , Richard Dominic WIETFELDT
CPC classification number: G06F13/4068 , H04L7/0066 , H04L7/042 , H04L7/0087 , G06F2213/40
Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.
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公开(公告)号:US20230231586A1
公开(公告)日:2023-07-20
申请号:US17580320
申请日:2022-01-20
Applicant: QUALCOMM Incorporated
Inventor: Xingyi HUA , Bassel HANAFI , Karthik TRIPURARI JAYARAMAN , Francesco GATTA
CPC classification number: H04B1/0483 , H03F1/565 , H04B2001/0416 , H03F2200/451
Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry implementing a low noise amplifier (LNA) with phase-shifting circuitry to achieve a continuous phase at the output of the LNA. One aspect is an amplifier including a high gain active path comprising active circuitry, and a low gain path comprising passive circuitry and phase-shifting circuitry. In one or more aspects, the phase-shifting circuitry is configured to shift a phase of an input signal within the low gain path such that the phase of an output signal outputted from the low gain path approximately matches a phase of an output signal outputted from the high gain active path. In at least one aspect, a gain of the high gain active path is higher than a gain of the low gain passive path.
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