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    Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
    22.
    发明授权
    Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer 有权

    公开(公告)号：US09779981B2

    公开(公告)日：2017-10-03

    申请号：US14715830

    申请日：2015-05-19

    Applicant: RF Micro Devices, Inc.

    Inventor： Julio C. Costa

    IPC: H01L21/00 ,  H01L21/762 ,  H01L27/12 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L29/786 ,  H01L23/31 ,  H01L21/56

    Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

    Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
    23.
    发明授权
    Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer 有权

    公开(公告)号：US09698045B2

    公开(公告)日：2017-07-04

    申请号：US14715830

    申请日：2015-05-19

    Applicant: RF Micro Devices, Inc.

    Inventor： Julio C. Costa

    IPC: H01L21/00 ,  H01L21/762 ,  H01L27/12 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L29/786 ,  H01L23/31 ,  H01L21/56

    Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

    Silicon-on-plastic semiconductor device and method of making the same
    24.
    发明授权
    Silicon-on-plastic semiconductor device and method of making the same 有权

    公开(公告)号：US09502328B2

    公开(公告)日：2016-11-22

    申请号：US14529870

    申请日：2014-10-31

    Applicant: RF Micro Devices, Inc.

    Inventor： Julio C. Costa ,  David M. Shuttleworth ,  Michael J. Antonell

    IPC: H01L23/373 ,  H01L27/12 ,  H01L23/48

    Abstract: A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer is disclosed. The semiconductor device includes a semiconductor stack structure with a first surface and a second surface wherein the second surface is on an opposite side of the semiconductor stack structure from the first surface. At least one device terminal is included in the semiconductor stack structure and at least one electrical contact extends from the second surface and is electrically coupled to the at least one device terminal. The semiconductor stack is protected by a polymer disposed on the first surface of the semiconductor stack. The polymer has high thermal conductivity and high electrical resistivity.

    RF SWITCH STRUCTURE HAVING REDUCED OFF-STATE CAPACITANCE
    25.
    发明申请
    RF SWITCH STRUCTURE HAVING REDUCED OFF-STATE CAPACITANCE 审中-公开
    具有降低非状态电容的RF开关结构

    公开(公告)号：US20150340322A1

    公开(公告)日：2015-11-26

    申请号：US14721531

    申请日：2015-05-26

    Applicant: RF Micro Devices, Inc.

    Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa

    IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

    CPC classification number: H01L23/5329 ,  H01L21/823475 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An RF switch structure having reduced off-state capacitance is disclosed. The RF switch structure includes an RF switch branch having at least three transistors coupled in series within a device layer. Inter-metal dielectric (IMD) layers are disposed over the device layer. At least one of the IMD layers has an effective dielectric constant that is lower than 3.9. In one exemplary embodiment, the IMD layers are made of silicon dioxide having micro-voids. In another exemplary embodiment, the IMD layers are made of silicon dioxide that includes carbon doping. In either exemplary embodiment, an effective dielectric constant ranges from about 3.9 to around 2.0. In another exemplary embodiment, the IMD layers are made of silicon dioxide having trapped air bubbles that provide an effective dielectric constant that ranges from about 2.0 to 1.1.

    Abstract translation: 公开了具有减小的截止状态电容的RF开关结构。 RF开关结构包括具有在器件层内串联耦合的至少三个晶体管的RF开关分支。 金属间电介质（IMD）层设置在器件层上。 至少一个IMD层具有低于3.9的有效介电常数。 在一个示例性实施例中，IMD层由具有微孔的二氧化硅制成。 在另一示例性实施例中，IMD层由包含碳掺杂的二氧化硅制成。 在任一示例性实施例中，有效介电常数范围为约3.9至约2.0。 在另一个示例性实施方案中，IMD层由具有捕获的气泡的二氧化硅制成，其提供范围为约2.0至1.1的有效介电常数。

    Encapsulated dies with enhanced thermal performance
    27.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US10020206B2

    公开(公告)日：2018-07-10

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

    Encapsulated dies with enhanced thermal performance
    28.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US09997376B2

    公开(公告)日：2018-06-12

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

    Encapsulated dies with enhanced thermal performance
    29.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US09960054B2

    公开(公告)日：2018-05-01

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

    Encapsulated dies with enhanced thermal performance
    30.
    发明授权
    Encapsulated dies with enhanced thermal performance 有权

    公开(公告)号：US09929024B2

    公开(公告)日：2018-03-27

    申请号：US15173037

    申请日：2016-06-03

    Applicant: RF Micro Devices, Inc.

    Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

    IPC: H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/00

    Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

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