3D MEMORY DEVICE
    21.
    发明申请

    公开(公告)号:US20210233583A1

    公开(公告)日:2021-07-29

    申请号:US17021409

    申请日:2020-09-15

    Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.

    MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE

    公开(公告)号:US20210090651A1

    公开(公告)日:2021-03-25

    申请号:US16999189

    申请日:2020-08-21

    Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

    STORAGE DEVICE CALCULATING OPTIMAL READ VOLTAGE USING DEGRADATION INFORMATION

    公开(公告)号:US20210043261A1

    公开(公告)日:2021-02-11

    申请号:US16810559

    申请日:2020-03-05

    Abstract: A storage device includes a first memory device including a plurality of memory blocks, and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage, to acquire the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits of each of the plurality of pages.

    ELECTRONIC DEVICE AND OPERATION METHOD THEREOF
    24.
    发明申请
    ELECTRONIC DEVICE AND OPERATION METHOD THEREOF 审中-公开
    电子设备及其操作方法

    公开(公告)号:US20160048270A1

    公开(公告)日:2016-02-18

    申请号:US14812346

    申请日:2015-07-29

    Abstract: An electronic device and an operation method thereof are provided. The method includes displaying information on a touch screen of the electronic device by operating a first application, displaying user interface of a second application, detecting an input through the user interface, displaying at least one recommendation object corresponding to the input among the information on the touch screen, at least partly in response to the input, receiving an input of selecting at least one of the at least one recommendation object, and displaying the recommendation object on the user interface, in response to the selecting input.

    Abstract translation: 提供了一种电子设备及其操作方法。 该方法包括通过操作第一应用程序来显示电子设备的触摸屏上的信息,显示第二应用的用户界面,通过用户界面检测输入,在信息中显示与输入相对应的至少一个推荐对象 触摸屏,至少部分地响应于输入,接收选择至少一个推荐对象中的至少一个的输入,以及响应于选择输入在用户界面上显示推荐对象。

    DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME

    公开(公告)号:US20230177986A1

    公开(公告)日:2023-06-08

    申请号:US17942775

    申请日:2022-09-12

    Abstract: A display panel in which a resistance structure is provided on a test pattern to prevent a circuit of the display panel from being damaged by static electricity introduced into the test pattern, and a display apparatus having the same are provided. The display panel includes: a substrate; a plurality of pixel circuits provided on the substrate and configured to drive a plurality of inorganic light emitting devices; a test line provided on the substrate and extending from an edge of the substrate; an insulating layer provided on the test line; and a resistance structure provided on the test line, the resistance structure including: at least two vertical interconnect accesses (vias) passing through the insulating layer; and a resistance layer provided on the insulating layer and extending between the at least two vias, wherein the at least two vias connect the test line and the resistance layer to each other, and the test line is discontinuous at an area between the at least two vias, and wherein the resistance layer is configured to receive, through one of the at least two vias, a current applied to the test line.

    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES

    公开(公告)号:US20230124303A1

    公开(公告)日:2023-04-20

    申请号:US18068337

    申请日:2022-12-19

    Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20230112891A1

    公开(公告)日:2023-04-13

    申请号:US17852614

    申请日:2022-06-29

    Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package includes a redistribution substrate that includes an organic dielectric layer and a metal pattern in the organic dielectric layer, and a semiconductor chip on the redistribution substrate. The organic dielectric layer has a maximum absorbance equal to or greater than about 0.04 at a first wavelength range, and a fluorescence intensity equal to or greater than about 4×103 at the first wavelength range. The first wavelength range is about 450 nm to about 650 nm.

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