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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, AN ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
    21.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, AN ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20240373632A1

    公开(公告)日：2024-11-07

    申请号：US18406913

    申请日：2024-01-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kang Lib Kim ,  Sungsu Moon ,  Sea Hoon Lee ,  Junhee Lim

    IPC: H10B43/27 ,  H01L23/522 ,  H10B43/40

    Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayers and gate electrodes and including a pad part having a stepwise structure on the contact region, a first dielectric layer covering the pad part of the stack structure, a second dielectric layer on the first dielectric layer, an interlayer capacitor between the first dielectric layer and the second dielectric layer, cell contact plugs penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and correspondingly connected to the gate electrodes, and lower and upper conductive lines penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and electrically connected to the interlayer capacitor.

    Resistive memory device controlling bitline voltage
    23.
    发明授权
    Resistive memory device controlling bitline voltage 有权

    公开(公告)号：US11430515B2

    公开(公告)日：2022-08-30

    申请号：US17036004

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Cheonan Lee ,  Satoru Yamada ,  Junhee Lim

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

    Semiconductor device for preventing defects between bit lines and channels
    24.
    发明授权
    Semiconductor device for preventing defects between bit lines and channels 有权

    公开(公告)号：US11049847B2

    公开(公告)日：2021-06-29

    申请号：US16734505

    申请日：2020-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kohji Kanamori ,  Yongseok Kim ,  Kyunghwan Lee ,  Junhee Lim ,  Jeehoon Han

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures. The first memory cell structure further includes first channel pads between the common bit lines and the first string select channel structures, and the second memory cell structure further includes second channel pads extending along the common bit lines.

    Three-dimensional semiconductor memory devices and methods of operating the same
    25.
    发明授权
    Three-dimensional semiconductor memory devices and methods of operating the same 有权

    公开(公告)号：US10971238B2

    公开(公告)日：2021-04-06

    申请号：US16714941

    申请日：2019-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kohji Kanamori ,  Yongseok Kim ,  Kyunghwan Lee ,  Junhee Lim

    IPC: G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.

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