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    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS
    23.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS 有权
    使用TRENCH隔离区域制造半导体器件以维持通道应力的方法

    公开(公告)号：US20150099335A1

    公开(公告)日：2015-04-09

    申请号：US14048282

    申请日：2013-10-08

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing LIU ,  Nicolas LOUBET

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203

    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.

    Abstract translation: 用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括在绝缘体上硅（SOI）晶片的半导体层中形成横向相邻的第一和第二有源区。 应力诱导层形成在第一有源区上方以赋予应力。 沟槽隔离区形成为包围应力诱导层的第一有源区和相邻部分。 去除应力诱导层，离开沟槽隔离区域以保持赋予第一有源区域的应力。

    VERTICAL TUNNELING FINFET
    24.
    发明申请
    VERTICAL TUNNELING FINFET 审中-公开

    公开(公告)号：US20200295187A1

    公开(公告)日：2020-09-17

    申请号：US16886193

    申请日：2020-05-28

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092

    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

    METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES
    26.
    发明申请
    METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES 审中-公开
    制造增强型UTBB FDSOI器件的方法和结构

    公开(公告)号：US20160190253A1

    公开(公告)日：2016-06-30

    申请号：US14942566

    申请日：2015-11-16

    Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Qing LIU ,  Thomas SKOTNICKI

    IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

    Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

    Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

    SEMI-FLOATING GATE FET
    27.
    发明申请
    SEMI-FLOATING GATE FET 审中-公开

    公开(公告)号：US20190252551A1

    公开(公告)日：2019-08-15

    申请号：US16355398

    申请日：2019-03-15

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing LIU ,  John H. Zhang

    IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

    CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

    Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

    VERTICAL TUNNELING FINFET
    28.
    发明申请
    VERTICAL TUNNELING FINFET 审中-公开

    公开(公告)号：US20180315850A1

    公开(公告)日：2018-11-01

    申请号：US16026663

    申请日：2018-07-03

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

    SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS
    29.
    发明申请
    SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS 审中-公开
    具有放松减少衬垫和相关方法的半导体器件

    公开(公告)号：US20150097212A1

    公开(公告)日：2015-04-09

    申请号：US14048232

    申请日：2013-10-08

    Applicant: STMicroelectronics, Inc.

    Inventor： Pierre MORIN ,  Qing LIU ,  Nicolas LOUBET

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/0653 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7842

    Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

    Abstract translation: 一种用于形成半导体器件的方法包括在应力半导体绝缘体晶片的应力半导体层上形成掩模层。 形成包围应力半导体层的隔离沟槽。 隔离沟槽延伸穿过掩模层并穿过SOI晶片的氧化物层。 绝缘体形成在隔离沟槽中。 在电介质体和应力半导体层的相邻侧壁上形成松弛减小衬垫。 应力半导体层上的掩模层被去除。

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