公开(公告)号：US20230018529A1

公开(公告)日：2023-01-19

申请号：US17948961

申请日：2022-09-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US20220140110A1

公开(公告)日：2022-05-05

申请号：US17574329

申请日：2022-01-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/66 ,  H01L29/775 ,  H01L21/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/41 ,  H01L21/265 ,  H01L21/8238

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US20210391356A1

公开(公告)日：2021-12-16

申请号：US17159013

申请日：2021-01-26

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L27/12 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/161 ,  H01L29/78 ,  H01L23/528 ,  H01L27/112 ,  H01L21/84 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/06

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20200373416A1

公开(公告)日：2020-11-26

申请号：US16988206

申请日：2020-08-07

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US20200295187A1

公开(公告)日：2020-09-17

申请号：US16886193

申请日：2020-05-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20180344186A1

公开(公告)日：2018-12-06

申请号：US16041140

申请日：2018-07-20

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: A61B5/04 ,  A61B5/00 ,  B82Y30/00 ,  G01N27/414

CPC classification number: A61B5/04001 ,  A61B5/6877 ,  A61B5/688 ,  B82Y30/00 ,  G01N27/4145 ,  Y10T29/4913

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

公开(公告)号：US20140183735A1

公开(公告)日：2014-07-03

申请号：US13731878

申请日：2012-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng XU ,  Walter Kleemeier ,  Cindy Goldberg

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract translation: 金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。 在电介质层中形成宽沟槽。 导电材料沉积在宽沟槽中。 在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

公开(公告)号：US20220328632A1

公开(公告)日：2022-10-13

申请号：US17852197

申请日：2022-06-28

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/786

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

公开(公告)号：US20200006350A1

公开(公告)日：2020-01-02

申请号：US16510612

申请日：2019-07-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  B82Y10/00

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US20190267404A1

公开(公告)日：2019-08-29

申请号：US16412357

申请日：2019-05-14

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L27/12 ,  H01L27/11 ,  H01L23/528 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/112 ,  H01L21/84

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.