公开(公告)号：US12193210B2

公开(公告)日：2025-01-07

申请号：US17719622

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Lee ,  Kijeong Kim ,  Jongcheon Kim ,  Donghwi Shin ,  Hyunsil Hong

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.

公开(公告)号：US20240063024A1

公开(公告)日：2024-02-22

申请号：US18497172

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H10B12/00

CPC classification number: H01L21/3088 ,  C23C16/45525 ,  C23C16/56 ,  C23C16/401 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3085 ,  H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US11245130B2

公开(公告)日：2022-02-08

申请号：US16517302

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeokjo Gwon ,  Jinkyu Kang ,  Kitae Park ,  Hyunchul Lee ,  Ryounghee Kim ,  Euncheol Do ,  Soojin Park ,  Sangmin Ji

IPC: H01M10/052 ,  H01M10/0567 ,  H01M50/44 ,  H01M50/46 ,  H01M50/403 ,  H01M50/411

Abstract: Provided herein is a lithium battery including: a cathode including a cathode active material; an anode including an anode active material; an electrolyte between the cathode and the anode; and a separator impregnated with the electrolyte, wherein the separator includes cellulose nanofibers, and wherein a differential scanning calorimetry (DSC) thermogram of the separator evinces an exothermic reaction peak, represented by a differential value (dH/dT), at a temperature in a range of about 150° C. to about 200° C.

公开(公告)号：US11211671B2

公开(公告)日：2021-12-28

申请号：US16196729

申请日：2018-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Junhwan Ku ,  Hyeokjo Gwon ,  Nagjong Kim ,  Chilhee Chung ,  Sangmin Ji ,  Jinkyu Kang ,  Changduk Kang ,  Ryounghee Kim ,  Minsang Kim ,  Euncheol Do ,  Kitae Park ,  Sunghaeng Lee

IPC: H01M50/44 ,  C08J5/22 ,  H01M10/052 ,  D21H11/18 ,  D21H21/22 ,  B32B21/02 ,  B32B21/10 ,  B32B5/18 ,  B32B5/32 ,  H01M50/429 ,  H01M50/449

Abstract: Provided herein are a porous film, a separator including the same, an electrochemical device including the separator, and a method of preparing the porous film. The porous film includes first cellulose nanofibers which is impregnated with a carbonate-based solvent-containing electrolyte solution and has a reaction heat of 150 J/g or less at a temperature ranging from about 30° C. to about 300° C., as measured by differential scanning calorimetry (DSC).

公开(公告)号：US10932125B2

公开(公告)日：2021-02-23

申请号：US16620993

申请日：2018-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinduck Lee ,  Hyunchul Lee

IPC: H04W12/00 ,  H04W8/18 ,  H04W12/06 ,  H04W88/02

Abstract: Various embodiments of the present invention relate to an electronic device for recognizing a SIM card. The electronic device may comprise: a display; a SIM card including at least one subscriber identification module; a processor electrically connected to the display and the SIM card; and a memory electrically connected to the processor, wherein in the memory stores instructions which, when executed, cause the processor to: identify whether a SIM lock is activated or not, on the basis of the at least one subscriber identification module included in the SIM card; and when it is identified that at least one subscriber identification module, the SIM lock of which has been deactivated, display a screen corresponding to the subscriber identification module, the SIM lock of which has been deactivated. Another embodiment is possible.

公开(公告)号：US10522366B2

公开(公告)日：2019-12-31

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.