公开(公告)号：US20240274754A1

公开(公告)日：2024-08-15

申请号：US18621969

申请日：2024-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyong MIN ,  Kyungwoon Jang ,  Jinyoung Kim ,  Changkyu Chung

IPC: H01L33/38 ,  H01L25/16 ,  H01L33/42

CPC classification number: H01L33/38 ,  H01L25/167 ,  H01L33/42 ,  H01L2933/0016

Abstract: A display module is provided and includes a driving substrate; first electrodes on the driving substrate, and light-emitting diodes (LEDs) including: semi-conductor layers; second electrodes respectively corresponding to the first electrodes; protrusions on each of the second electrodes; and metal layers on the protrusions, each of the metal layers connected to one of the second electrodes. The display module further includes a non-conductive film layer between the driving substrate and the LEDs. The first electrodes and the second electrodes are connected by the metal layers.

公开(公告)号：US12045132B2

公开(公告)日：2024-07-23

申请号：US18156893

申请日：2023-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongmin Shin ,  Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo

IPC: G06F11/10 ,  H03M13/45

CPC classification number: G06F11/1068 ,  H03M13/45

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

公开(公告)号：US11804280B2

公开(公告)日：2023-10-31

申请号：US17749607

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C16/28 ,  G11C7/10 ,  G11C8/18 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11775203B2

公开(公告)日：2023-10-03

申请号：US17376437

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin ,  Woohyun Kang ,  Shinho Oh

IPC: G06F3/00 ,  G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/08

Abstract: A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

公开(公告)号：US20230154552A1

公开(公告)日：2023-05-18

申请号：US17847545

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Kim ,  Jinyoung Kim ,  Sehwan Park ,  Seoyoung Lee ,  Jisang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08

Abstract: Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.

公开(公告)号：US11514997B2

公开(公告)日：2022-11-29

申请号：US17156801

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Sangwan Nam

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

公开(公告)号：US11500706B2

公开(公告)日：2022-11-15

申请号：US17233816

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong Kim ,  Jinyoung Kim ,  Sehwan Park ,  Hyun Seo ,  Sangwan Nam

IPC: G11C7/00 ,  G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data, calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

公开(公告)号：US11482263B2

公开(公告)日：2022-10-25

申请号：US17239647

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/18 ,  G11C8/08

Abstract: A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.

公开(公告)号：US20220231064A1

公开(公告)日：2022-07-21

申请号：US17648294

申请日：2022-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGWOO CHUNG ,  Sooeon Kim ,  Jinyoung Kim ,  Hyehi Shin ,  Eungkyu Lee ,  Jeongrae Jo

IPC: H01L27/146

Abstract: An image sensor includes a substrate that includes a plurality of photoelectric conversion devices, an insulating structure disposed on the substrate, a grid pattern structure disposed on the insulating structure, a plurality of color filters disposed on the insulating structure, and a plurality of microlenses disposed on the plurality of color filters. The grid pattern structure includes a first pattern portion and a plurality of second pattern portions spaced apart from the first pattern portion. The first pattern portion is disposed between proximate pairs of color filters among the plurality of color filters. An entire side surface of each second pattern portion of the plurality of second pattern portions is respectively surrounded by a color filter from among the first to third color filters.

公开(公告)号：US11380405B2

公开(公告)日：2022-07-05

申请号：US16810559

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeduk Yu ,  Jinyoung Kim

IPC: G11C29/00 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G06F3/06 ,  G11C16/08 ,  G06F11/10 ,  G11C16/24

Abstract: A storage device includes a first memory device including a plurality of memory blocks, and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage, to acquire the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits of each of the plurality of pages.