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公开(公告)号：US09105792B2
公开(公告)日：2015-08-11
申请号：US13647902
申请日：2012-10-09
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/22 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L21/02658 , H01L29/2003 , H01L29/205 , H01L29/34 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L33/007 , H01L33/06 , H01L33/10 , H01L33/12 , H01L33/24 , H01L33/32 , H01L2933/0091
Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
Abstract translation: 提供了使用具有图案化表面的层以改善半导体层生长的器件的方法，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。
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公开(公告)号：US20140110754A1
公开(公告)日：2014-04-24
申请号：US13692191
申请日：2012-12-03
Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Michael Shur
CPC classification number: H01L33/06 , H01L21/0237 , H01L21/02433 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L29/151 , H01L33/007 , H01L33/025
Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
Abstract translation: 提供了一种用于制造半导体结构的解决方案。 半导体结构包括使用一组外延生长周期在衬底上生长的多个半导体层。 在每个外延生长周期期间，生长具有拉伸应力或压缩应力之一的第一半导体层，然后直接在第一半导体层上生长具有另一个的拉伸应力或压缩应力的第二半导体层。
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公开(公告)号：US20130270519A1
公开(公告)日：2013-10-17
申请号：US13863423
申请日：2013-04-16
Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
Inventor： Wenhong Sun , Alexander Dobrinsky , Maxim S Shatalov , Jinwei Yang , Michael Shur , Remigijus Gaska
IPC: H01L33/06
CPC classification number: H01L33/06 , H01L21/02389 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L33/0066 , H01L33/0075 , H01L33/04
Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
Abstract translation: 提供了包括一个或多个精细结构区域的发光异质结构。 发光异质结构可以包括与多个量子阱交替的多个势垒。 一个或多个障碍物和/或量子阱包括精细结构区域。 精细结构区域包括以增长或横向方向中的至少一个布置的多个子量表特征。
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公开(公告)号：US10460952B2
公开(公告)日：2019-10-29
申请号：US16022939
申请日：2018-06-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L21/308 , H01L29/20 , H01L21/02 , H01L29/66 , H01L29/15 , H01L33/00 , H01L33/12 , H01L33/22 , H01L33/32
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
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25.发明授权公开(公告)号：US10211048B2
公开(公告)日：2019-02-19
申请号：US13756806
申请日：2013-02-01
Applicant: Sensor Electronic Technology, Inc.
Inventor： Wenhong Sun , Rakesh Jain , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Michael Shur
Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
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Patent Agency Ranking
公开(公告)号：US20180323071A1
公开(公告)日：2018-11-08
申请号：US16022939
申请日：2018-06-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
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公开(公告)号：US20180269355A1
公开(公告)日：2018-09-20
申请号：US15989275
申请日：2018-05-25
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/12
CPC classification number: H01L33/12 , C30B25/04 , C30B25/183 , C30B29/406 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/205 , H01L29/518 , H01L29/7786 , H01L29/7787 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/10 , H01L33/145 , H01L33/22 , H01L33/24 , H01L33/32 , H01L33/405 , H01L2933/0091
Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
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公开(公告)号：US10050175B2
公开(公告)日：2018-08-14
申请号：US15797263
申请日：2017-10-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L27/15 , H01L31/072 , H01L33/06 , H01L21/02 , H01L29/778 , H01L33/12 , H01L33/24 , H01L33/32 , H01L29/20 , H01L29/51 , H01L33/22
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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公开(公告)号：US20180047870A1
公开(公告)日：2018-02-15
申请号：US15797263
申请日：2017-10-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/06 , H01L33/12 , H01L29/778 , H01L33/24 , H01L21/02 , H01L33/32 , H01L33/22 , H01L29/20 , H01L29/51
CPC classification number: H01L33/06 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/518 , H01L29/7786 , H01L33/12 , H01L33/22 , H01L33/24 , H01L33/32 , H01L2933/0083 , H01L2933/0091
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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公开(公告)号：US20170345968A1
公开(公告)日：2017-11-30
申请号：US15662675
申请日：2017-07-28
Applicant: Sensor Electronic Technology, Inc.
Inventor： Wenhong Sun , Alexander Dobrinsky , Maxim S. Shatalov , Jinwei Yang , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/06 , H01L21/02389 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L33/0066 , H01L33/0075 , H01L33/04
Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
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