公开(公告)号：US09966965B2

公开(公告)日：2018-05-08

申请号：US15370742

申请日：2016-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Rangakrishnan Srinivasan ,  Francesco Barale

IPC: H03L7/06 ,  H03L7/183 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/183 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/06

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

公开(公告)号：US09948313B1

公开(公告)日：2018-04-17

申请号：US15383483

申请日：2016-12-19

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi

IPC: H01G4/008 ,  H03L7/099 ,  H03L7/085 ,  H01L49/02

CPC classification number: H03L7/099 ,  H01L28/60 ,  H03L7/0893 ,  H03L7/193

Abstract: Apparatus and methods are disclosed that utilize magnetically differential loop filter capacitor elements that are physically positioned adjacent voltage-controlled oscillator (VCO) inductor/s in the device layout of a phase locked loop (PLL) circuit. Such a PLL circuit may be employed, for example, to produce a PLL output signal for RF receivers, RF transmitters, RF transceivers and any other type of circuit configured to utilize a PLL output signal having a phase that is based on the phase of an input signal.

公开(公告)号：US09712176B1

公开(公告)日：2017-07-18

申请号：US15179847

申请日：2016-06-10

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Mustafa H. Koroglu

IPC: H03L7/06 ,  H03L7/183 ,  H04L7/033 ,  H04B7/02

CPC classification number: H03L7/0893 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/06

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is lower than the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

公开(公告)号：US20150147992A1

公开(公告)日：2015-05-28

申请号：US14612346

申请日：2015-02-03

Applicant: Silicon Laboratories Inc.

Inventor： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager ,  Abdulkerim L. Coban

IPC: H04B1/28 ,  H04L27/148

CPC classification number: H04B1/28 ,  H03H11/04 ,  H04B1/30 ,  H04L27/148 ,  H04N5/455 ,  H04N5/50

Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.

Abstract translation: 在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。 跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。 集成电感器包括形成在多个金属层中的多个绕组。 可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。 混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。

公开(公告)号：US08725099B2

公开(公告)日：2014-05-13

申请号：US13663832

申请日：2012-10-30

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Alessandro Piovaccari

IPC: H04B1/16

CPC classification number: H03D7/00 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0084 ,  H03D2200/0086

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

公开(公告)号：US11444627B1

公开(公告)日：2022-09-13

申请号：US17549314

申请日：2021-12-13

Applicant: Silicon Laboratories Inc.

Inventor： Rangakrishnan Srinivasan ,  Michael Wu ,  Francesco Barale ,  John Khoury ,  Aslamali A. Rafi

IPC: H03L7/099 ,  G06F1/08 ,  H03L7/093

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

公开(公告)号：US20210391864A1

公开(公告)日：2021-12-16

申请号：US16901814

申请日：2020-06-15

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Timothy A. Monk ,  William Anker ,  Srisai Rao Seethamraju

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/14 ,  H03L7/197

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

公开(公告)号：US20170359076A1

公开(公告)日：2017-12-14

申请号：US15370742

申请日：2016-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Rangakrishnan Srinivasan ,  Francesco Barale

IPC: H03L7/183 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/183 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/06

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

公开(公告)号：US20160241285A1

公开(公告)日：2016-08-18

申请号：US14625324

申请日：2015-02-18

Applicant: SILICON LABORATORIES INC.

Inventor： Aslamali A. Rafi

IPC: H04B1/12

CPC classification number: H04B1/123 ,  H04B1/28

Abstract: A receiver comprises a passive gain stage having an input to receive an in-going radio frequency (RF) signal and a gain control signal to produce an adjusted in-going RF signal, a sliced LNA stage comprising a plurality of LNAs coupled to receive the in-going RF signal. Each LNA includes an adjustable source degeneration circuit for receiving a plurality of gain selection and control signals and an output port to produce an amplified in-going RF signal. A mixer is coupled to receive at least one of the amplified in-going RF signals produced by the sliced LNA stage and is configured to produce a converted signal at another frequency. A PGA is coupled to receive the down-converted signal and produces an amplified in-going signal.

Abstract translation: 接收机包括无源增益级，其具有用于接收正在进行的射频（RF）信号的输入和增益控制信号以产生经调整的进行中的RF信号;切片的LNA级，包括耦合以接收所述RF信号的多个LNA 正在进行的RF信号。 每个LNA包括可调节的源极退化电路，用于接收多个增益选择和控制信号以及输出端口以产生放大的进行中的RF信号。 耦合混频器以接收由限幅LNA级产生的放大的正在进行的RF信号中的至少一个，并且被配置为在另一个频率处产生转换的信号。 PGA被耦合以接收经下变频的信号并产生放大的进行信号。

公开(公告)号：US09319027B1

公开(公告)日：2016-04-19

申请号：US14573144

申请日：2014-12-17

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi

IPC: H04B1/10 ,  H04B17/21 ,  H03H11/04 ,  H03F3/19 ,  H03F3/45 ,  H03H11/32 ,  H03L7/099 ,  H04B1/26

CPC classification number: H03H11/0466 ,  H03F3/19 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45964 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45396 ,  H03F2203/45422 ,  H03L7/099 ,  H04B1/28 ,  H04B17/21

Abstract: In an example, apparatus comprises: a low noise amplifier (LNA) including a first transconductor having an input to receive a differential input radio frequency (RF) signal and an output to output a differential amplified RF signal to a RF signal path; and a second transconductor having an input coupled to a first common mode node and a second common mode node to receive a test tone signal and an output to output an amplified test tone signal to the RF signal path.

Abstract translation: 在一个示例中，装置包括：低噪声放大器（LNA），包括具有用于接收差分输入射频（RF）信号的输入端的第一跨导器和输出以将差分放大RF信号输出到RF信号路径; 以及第二跨导体，其具有耦合到第一共模节点和第二共模节点的输入，以接收测试音信号和输出，以将放大的测试音信号输出到RF信号路径。