公开(公告)号：US09515367B2

公开(公告)日：2016-12-06

申请号：US14939128

申请日：2015-11-12

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Robert Floyd Payne ,  Gerd Schuppener ,  Baher Haroun

IPC: H01P5/00 ,  H01Q13/00 ,  H01P3/16 ,  H01P5/08 ,  G02B6/44 ,  H01P11/00 ,  H01Q1/50 ,  H01Q19/10 ,  H04B1/40 ,  H01Q19/30 ,  H01P3/12 ,  H01P5/107 ,  H01P5/18

CPC classification number: H01P3/16 ,  G02B6/4416 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/165 ,  H01P5/00 ,  H01P5/087 ,  H01P5/107 ,  H01P5/184 ,  H01P11/001 ,  H01P11/002 ,  H01Q1/50 ,  H01Q19/108 ,  H01Q19/30 ,  H04B1/40 ,  Y10T29/49016 ,  Y10T29/49826

Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.

Abstract translation: 金属波导安装在多层基板上。 金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到 接触多层基板。 锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。

公开(公告)号：US09350063B2

公开(公告)日：2016-05-24

申请号：US13854943

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Robert Floyd Payne

IPC: H01P3/16 ,  H01Q13/00 ,  H01P3/12 ,  H05K1/02

CPC classification number: H01P3/16 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P1/04 ,  H01P3/121 ,  H01Q13/00 ,  H05K1/0239 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09618 ,  H05K2201/10098 ,  Y10T29/49826 ,  Y10T29/49908

Abstract: A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end.

Abstract translation: 电介质波导（DWG）具有具有第一介电常数值的介质芯构件。 围绕介电芯构件的包层具有低于第一介电常数的第二介电常数值。 DWG的配合端构造成非平面形状，用于与具有匹配的非平面形配合端的第二DWG配合。

公开(公告)号：US20150295298A1

公开(公告)日：2015-10-15

申请号：US14555545

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Robert Floyd Payne ,  Gerd Schuppener ,  Juan Alejandro Herbsommer

IPC: H01P3/16 ,  H01Q19/18 ,  H01P11/00 ,  H01Q1/50

CPC classification number: H01P3/16 ,  H01P11/006

Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.

Abstract translation: 数字系统具有形成在多层基板内的介质芯波导。 电介质波导具有形成在芯层中的纵向介质芯构件，其具有两个相邻的纵向侧，每个纵向侧通过形成在芯层中的对应的狭缝部分与芯层分离。介电芯构件具有第一介电常数值。 包层包围由顶层形成的介质芯构件，底层填充芯层的槽部分。 包层具有低于第一介电常数值的介电常数值。

公开(公告)号：US11799184B2

公开(公告)日：2023-10-24

申请号：US17140858

申请日：2021-01-04

Applicant: Texas Instruments Incorporated

Inventor： Baher Haroun ,  Juan Alejandro Herbsommer ,  Gerd Schuppener ,  Swaminathan Sankaran

IPC: H01P5/08 ,  H01P11/00 ,  H01P3/16

CPC classification number: H01P5/087 ,  H01P3/16 ,  H01P11/001

Abstract: An interposer acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect and establishes two well-defined reference planes that can be optimized independently. The interposer includes a block of material having: a first interface region to interface with an antenna coupled to an integrated circuit (IC); and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.

公开(公告)号：US20230238410A1

公开(公告)日：2023-07-27

申请号：US17586001

申请日：2022-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Edwards ,  Rahmi Hezar ,  Udumbara Wijesinghe ,  Wenjuan Fan ,  Gerd Schuppener

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14643 ,  H01L27/1463 ,  H01L27/14685

Abstract: The present disclosure generally relates to a surface grating in a photodetector device. In an example, a semiconductor device structure includes a photodetector device. The photodetector device includes one or more photodiodes disposed in or over a semiconductor substrate, and includes a surface grating disposed at a respective surface of each photodiode of the one or more photodiodes. The surface grating has one or more periodicities. Each periodicity of the one or more periodicities has a period that is along a direction parallel to a first lateral direction across the semiconductor substrate and that is equal to or less than half of a dimension of at least one photodiode of the one or more photodiodes along a direction parallel to the first lateral direction. The one or more periodicities includes multiple different pitches.

公开(公告)号：US11171636B2

公开(公告)日：2021-11-09

申请号：US16585155

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Tolga Dinc ,  Salvatore Luciano Finocchiaro ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03K5/02 ,  H03K5/26 ,  G01R25/04 ,  H03H7/01 ,  H03K5/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

公开(公告)号：US20210203331A1

公开(公告)日：2021-07-01

申请号：US16731800

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Salvatore Luciano Finocchiaro ,  Timothy Schmidl ,  Tolga Dinc ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

IPC: H03L7/099 ,  H03L7/08 ,  H03L7/093 ,  H04B1/40 ,  H04L7/033 ,  H04L27/12 ,  H04L27/14

Abstract: In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90° to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.

公开(公告)号：US10979277B1

公开(公告)日：2021-04-13

申请号：US16731823

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy Mark Schmidl ,  Swaminathan Sankaran ,  Gerd Schuppener ,  Salvatore Luciano Finocchiaro ,  Siraj Akhtar ,  Tolga Dinc ,  Anand Ganesh Dabak ,  Baher Haroun

IPC: H04L27/38 ,  H04L25/03 ,  H04B7/005 ,  H03L7/191 ,  H03B5/32 ,  H03L7/087

Abstract: In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

公开(公告)号：US20190267979A1

公开(公告)日：2019-08-29

申请号：US16410508

申请日：2019-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

IPC: H03K5/156 ,  H02M3/07

Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

公开(公告)号：US20190097593A1

公开(公告)日：2019-03-28

申请号：US15716091

申请日：2017-09-26

Applicant: Texas Instruments Incorporated

Inventor： Jikai Chen ,  Gerd Schuppener ,  Yanli Fan

IPC: H03F3/45 ,  H03F1/26

Abstract: An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.