公开(公告)号：US20190172946A1

公开(公告)日：2019-06-06

申请号：US15830856

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/285 ,  H01L21/74

Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

公开(公告)号：US20180269317A1

公开(公告)日：2018-09-20

申请号：US15988543

申请日：2018-05-24

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L29/7811 ,  H01L21/266 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/4916 ,  H01L29/66727

Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.

公开(公告)号：US09947783B2

公开(公告)日：2018-04-17

申请号：US15135154

申请日：2016-04-21

Applicant: Texas Instruments Incorporated

Inventor： Chin-Yu Tsai ,  Imran Khan ,  Xiaoju Wu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66681 ,  H01L29/7833

Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

公开(公告)号：US12199091B2

公开(公告)日：2025-01-14

申请号：US17503877

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/06 ,  H01L49/02

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US11296075B2

公开(公告)日：2022-04-05

申请号：US16118648

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US10580890B2

公开(公告)日：2020-03-03

申请号：US15830856

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L21/74 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/285

Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

公开(公告)号：US20180130798A1

公开(公告)日：2018-05-10

申请号：US15865321

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu ,  C. Matthew Thompson

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/1033

Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.

公开(公告)号：US20170257088A1

公开(公告)日：2017-09-07

申请号：US15386252

申请日：2016-12-21

Applicant: Texas Instruments Incorporated

Inventor： Xiaoju Wu ,  Rajesh Keloth ,  Sudheer Prasad

IPC: H03K17/08 ,  H01L29/417 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

CPC classification number: H03K17/08 ,  H01L27/0262 ,  H01L29/063 ,  H01L29/41775 ,  H01L29/7835 ,  H03K17/08142 ,  H03K17/6874 ,  H03K2217/0018

Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

公开(公告)号：US20250120169A1

公开(公告)日：2025-04-10

申请号：US18982600

申请日：2024-12-16

Applicant: Texas Instruments Incorporated

Inventor： Robert Martin Higgins ,  Xiaoju Wu ,  Li Wang ,  Venugopal Balakrishna Menon

IPC: H01L27/06 ,  H01L21/762

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

公开(公告)号：US20220189949A1

公开(公告)日：2022-06-16

申请号：US17684774

申请日：2022-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.