公开(公告)号：US06333639B1

公开(公告)日：2001-12-25

申请号：US09599559

申请日：2000-06-23

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: H03K19003

CPC classification number: H03K19/017581

Abstract: An apparatus and method for independently adjusting or calibrating the characteristics of multiple drivers for output buffer circuits without significantly increasing the associated necessary circuitry is disclosed. A central control logic circuit initiates the calibration process of the drivers. A serial communication link is provided between the control logic and each of the output drivers. The serial link reduces the number of lines that are required to communicate between the central control logic and the multiple output drivers. The output drivers can be calibrated one at a time, and a handoff is made from one driver to the next to start the calibration of the subsequent driver.

Abstract translation: 公开了用于独立地调整或校准用于输出缓冲器电路的多个驱动器的特性而不显着增加相关联的必要电路的装置和方法。 中央控制逻辑电路启动驱动程序的校准过程。 在控制逻辑和每个输出驱动器之间提供串行通信链路。 串行链路减少了在中央控制逻辑和多个输出驱动器之间通信所需的行数。 可以一次一个地校准输出驱动器，并且从一个驱动器到另一个驱动器进行切换以开始后续驱动器的校准。

公开(公告)号：US06327192B1

公开(公告)日：2001-12-04

申请号：US09685966

申请日：2000-10-10

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G11C700

CPC classification number: G11C8/10 ,  G11C7/1042 ,  G11C7/12

Abstract: A memory device has address, data, and control buses, and a memory-cell array including a number of memory cells arranged in rows and columns, each memory cell operable to store a bit of data. A row address decoder circuit is adapted to receive a row address applied on the address bus and operates to decode the row address and activate a row of memory cells corresponding to the decoded row address. A column address decoder circuit is adapted to receive a column address applied on the address bus and operates to decode the column address and access a plurality of memory cells in the activated row. The data stored in the plurality of memory cells in the activated row is defined as a block of data. A precharge circuit is coupled to the memory-cell array and operates, when activated, to precharge and equilibrate the memory-cell array. A block read latch circuit operates to latch a first block of data accessed in the memory-cell array corresponding to first decoded row and column addresses, and to sequentially transfer subblocks of the first block of data onto the data bus. The memory device operates such that after the first block of data is latched in the block read latch, the precharge circuit first precharges and equilibrates the memory-cell array, and the row and column decoder circuits then decode second row and column addresses such that the column address decoder circuit accesses a second block of data corresponding to the second row and column addresses before the block read latch circuit has completed sequentially transferring all the subblocks of the first block of data onto the data bus. The memory device may further include a block write latch circuit adapted to sequentially receive on the data bus subblocks of data contained in a first block of data to be written to the memory-cell array.

Abstract translation: 存储器设备具有地址，数据和控制总线以及包括以行和列布置的多个存储器单元的存储单元阵列，每个存储器单元可操作以存储一位数据。 行地址解码器电路适于接收施加在地址总线上的行地址，并且操作以解码行地址并激活对应于解码行地址的一行存储单元。 列地址解码器电路适于接收施加在地址总线上的列地址，并且操作以解码列地址并访问激活行中的多个存储单元。 存储在激活行中的多个存储器单元中的数据被定义为数据块。 预充电电路耦合到存储单元阵列，并在被激活时操作以预充电和平衡存储单元阵列。 块读取锁存电路用于锁存对应于第一解码的行和列地址的存储单元阵列中访问的第一数据块，并将第一数据块的子块顺序传送到数据总线上。 存储器件操作使得在第一块数据被锁存在块读取锁存器中之后，预充电电路首先对存储单元阵列进行预充电和平衡，然后行和列解码器电路解码第二行和列地址，使得 列地址解码器电路在块读取锁存电路已经完成顺序地将第一数据块的所有子块顺序地传送到数据总线之前访问对应于第二行和列地址的第二数据块。 存储器件还可以包括块写入锁存电路，其适于在数据总线上顺序接收包含在要写入存储单元阵列的第一数据块中的数据的子块。

公开(公告)号：US06302719B1

公开(公告)日：2001-10-16

申请号：US09400126

申请日：1999-09-21

Applicant: David J. Corisis ,  Jerry M. Brooks ,  Terry R. Lee

Inventor： David J. Corisis ,  Jerry M. Brooks ,  Terry R. Lee

IPC: H01R1362

CPC classification number: H05K7/1023 ,  H01R12/7029 ,  H01R12/7064 ,  H01R12/707 ,  H05K3/301

Abstract: A semiconductor package for vertically surface mounting to a printed circuit board having retention apparatus for holding the package thereto.

公开(公告)号：US06215183B1

公开(公告)日：2001-04-10

申请号：US09505493

申请日：2000-02-16

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

IPC: H01L2334

CPC classification number: H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

公开(公告)号：US5944199A

公开(公告)日：1999-08-31

申请号：US978397

申请日：1997-11-25

Applicant: David J. Corisis ,  Walter L. Moden ,  Terry R. Lee

Inventor： David J. Corisis ,  Walter L. Moden ,  Terry R. Lee

IPC: H01L25/10 ,  H05K3/30 ,  A47F55/00

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2924/0002

Abstract: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card. The packages may also be braced against one another. The structure is particularly well adapted to supporting vertical surface mount packages at a point spaced from the point where they connect to a printed circuit board or card.

Abstract translation: 用于支持集成电路封装以防止封装在其与印刷电路板或卡的连接处的机械故障的系统包括将封装支撑到板或卡。 包装也可以相互支撑。 该结构特别适合于在与连接到印刷电路板或卡的点间隔开的点处支撑垂直表面安装封装。

公开(公告)号：USRE35847E

公开(公告)日：1998-07-14

申请号：US675728

申请日：1996-07-03

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G11C7/10 ,  H02H3/14

CPC classification number: G11C7/1006 ,  G11C7/1048 ,  G11C7/1051

Abstract: The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device which is sourcing current to pull the data line low. The device is turned off when the potential on the low data line has transitioned to the trip point of the output data latch. The circuit of the invention senses the transition and provides the self terminating signal to the current source.

Abstract translation: 本发明是与动态随机存取存储器（DRAM）或静态随机存取存储器（SRAM）装置相关的自终止辅助器触发器缓冲器电路。 本发明关闭了提供电流以将数据线拉低的装置。 当低数据线上的电位已经转换到输出数据锁存器的跳变点时，该器件被关闭。 本发明的电路感测到转换并将自终止信号提供给电流源。

公开(公告)号：US5276642A

公开(公告)日：1994-01-04

申请号：US730366

申请日：1991-07-15

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C11/409 ,  G11C7/00

Abstract: The invention is a method for implementing a split read/write operation in a multiple write enable dynamic random access memory device. A split read/write operation is an operation where the data in at least one bank is read while the data is being written to at least one remaining bank, all banks accessed by the same address. The method of the invention also implements writes and reads to all of the banks, a write to at least one bank, and a read to at least one bank. In instances where all of the banks are not written, the banks not being written are refreshed; and in instances where all of the banks are not being read, the banks not being read are masked for a write. The invention also provides individual masking of selected memory arrays in both write and read operations.

Abstract translation: 本发明是一种用于在多写入使能动态随机存取存储器件中实现分离读/写操作的方法。 分割读/写操作是在数据被写入至少一个剩余存储体的同时读取至少一个存储体中的数据的操作，所有由相同地址访问的存储体。 本发明的方法还实现对所有银行的写入和读取，对至少一个银行的写入以及对至少一个银行的读取。 在所有银行不写的情况下，不写的银行刷新; 并且在所有银行都没有被阅读的情况下，不被读取的银行被掩盖以进行写入。 本发明还在写入和读取操作中提供对所选择的存储器阵列的单独掩蔽。

公开(公告)号：US08892974B2

公开(公告)日：2014-11-18

申请号：US13470613

申请日：2012-05-14

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G01R31/28 ,  H04L1/24 ,  H04B10/25 ,  H04L7/04 ,  H04L1/00

CPC classification number: H04B10/2504 ,  H04L1/0001 ,  H04L1/242 ,  H04L7/043

Abstract: A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract translation: 一种动态调整通信网络链路控制参数的方法。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。

公开(公告)号：US08687446B2

公开(公告)日：2014-04-01

申请号：US12176710

申请日：2008-07-21

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C8/18

CPC classification number: G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5002

Abstract: A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.

Abstract translation: 半导体器件包括具有动态存储单元的存储器阵列。 在自刷新测试模式中，自刷新测试模式控制器监视和/或控制半导体器件中的各种块和内部信号。 自刷新测试模式控制器可以通过包括一个或多个DQ线和/或一个或多个地址线的各种导体与远程测试设备进行通信。

公开(公告)号：US08200884B2

公开(公告)日：2012-06-12

申请号：US13163974

申请日：2011-06-20

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G06F12/06

CPC classification number: G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract translation: 计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。 存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。