公开(公告)号：US09331123B2

公开(公告)日：2016-05-03

申请号：US14274601

申请日：2014-05-09

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Avi Strum

IPC: H01L43/02 ,  H01L27/22 ,  H03K19/003 ,  G11C11/15

CPC classification number: H01L27/228 ,  G11C11/15 ,  H01L43/02 ,  H03K3/45 ,  H03K19/00369 ,  H03K19/18

Abstract: A logic unit for security engines or content addressable memory including Magnetic Tunnel Junction (MTJ) elements connected in series to form a NAND-type string, where each MTJ element includes a storage layer and a sense layer having different anti-ferromagnetic materials respectively having higher and lower blocking temperatures. During write/program, the string is heated above the higher blocking temperature, and magnetic fields are used to store bit values of a confidential logical pattern in the storage layers. The string is then cooled to an intermediate temperature between the higher and lower blocking temperatures and the field lines turned off to store bit-bar (opposite) values in the sense layers. During a pre-compare operation, the MTJ elements are heated to the intermediate temperature, and an input logical pattern is stored in the sense layers. During a compare operation, with the field lines off, a read current is passed through the string and measured.

Abstract translation: 一种用于安全引擎或内容可寻址存储器的逻辑单元，包括串联连接的磁隧道结（MTJ）元件，以形成NAND型串，其中每个MTJ元件包括存储层和具有不同反铁磁材料的感测层，分别具有较高的 和较低的封闭温度。 在写入/编程期间，将串被加热到较高的阻塞温度以上，并且使用磁场来存储存储层中的机密逻辑图案的位值。 然后将该串冷却到较高和较低的阻断温度之间的中间温度，并且切断电场线以在感应层中存储位（相反）的值。 在预比较操作期间，MTJ元件被加热到中间温度，并且输入逻辑图案被存储在感测层中。 在比较操作期间，当场线关闭时，读取电流通过该字符串并进行测量。

公开(公告)号：US09330748B2

公开(公告)日：2016-05-03

申请号：US14274609

申请日：2014-05-09

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Avi Strum

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C15/02

Abstract: A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string.

Abstract translation: 现场对位式比较操作使用一系列磁隧道结（MTJ）元件，包括具有不同反铁磁结构的存储层和感测层，分别具有较高和较低的阻挡温度。 机密数据通过加热高于更高阻挡温度的元件，然后使用场线在第一存储磁化方向上定向存储和感测层，将MTJ元件的存储层写入到存储层中。 然后将元件冷却到较高和较低阻断温度之间的中间温度，并且将场线关闭，将感应层设置为与第一方向相反的初步储存磁化方向。 在预比较阶段期间，通过加热到中间温度将输入逻辑图案写入感测层。 在比较操作期间，当场线被关闭时，通过将读取的电流通过串来检测MTJ串的电阻。

公开(公告)号：US09082867B2

公开(公告)日：2015-07-14

申请号：US13756481

申请日：2013-01-31

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan ,  Micha Gutman

IPC: H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/66833

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract translation: 用于CMOS IC的具有成本效益的SONOS（CEONOS）非易失性存储器（NVM）单元，其中CEONOS NVM单元需要两个或三个附加掩模，但是使用用于形成的相同的标准CMOS流程 NMOS晶体管。 该单元类似于NMOS单元，但是包括替代标准NMOS栅极氧化物并用于存储NVM数据的氧化物 - 氮化物 - 氧化物（ONO）层。 这些电池采用特殊的源极/漏极工程，包括袋式注入和轻掺杂漏极扩展，这有助于使用低电压（例如5V）对CEONOS NVM单元进行编程/擦除。 使用相应的NMOS工艺形成多晶硅栅极，源极/漏极接触和金属化。 CEONOS NVM单元以空间有效的X阵列图案排列，使得每组四个单元共享漏极扩散和三个位线。 编程涉及标准CHE注入或脉冲搅拌界面基板热电子注入（PAISHEI）。

公开(公告)号：US20140273332A1

公开(公告)日：2014-09-18

申请号：US13831473

申请日：2013-03-14

Applicant: Yissum Research Development Company of The Hebrew Univsersity of Jerusalem Ltd. ,  TOWER SEMICONDUCTOR LTD.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Irit Chen-Zamero ,  Ora Eli ,  Micha Asscher ,  Amir Saar

IPC: H01L31/042

CPC classification number: H01L31/047 ,  H01L27/142 ,  H01L31/075 ,  H01L31/1804 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P− epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.

Abstract translation: 通过在硅岛上形成侧向P-I-N光敏二极管，通过由RIE执行的沟槽横向隔离，并通过多孔硅区域从下面的支撑衬底形成光电器件。 P +和N +掺杂区形成在P-外延层中，将沟槽通过外延层蚀刻成P +衬底，在沟槽壁上形成保护层（例如SiN），然后形成多孔硅（例如， 使用HF溶液）在通过P +底物横向生长并在岛下合并的沟槽中。 该方法被用于在CMOS IC器件上形成低成本嵌入式光伏阵列，或者通过蚀刻穿过多孔硅来将器件与P +衬底分离，以产生用于太阳能源的低成本，高压太阳能阵列，例如， 太阳能集中器

公开(公告)号：US20140209994A1

公开(公告)日：2014-07-31

申请号：US13756481

申请日：2013-01-31

Applicant: TOWER SEMICONDUCTOR LTD.

Inventor： Yakov Roizin ,  Evgeny Pikhay ,  Vladislav Dayan ,  Micha Gutman

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/66833

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract translation: 用于CMOS IC的具有成本效益的SONOS（CEONOS）非易失性存储器（NVM）单元，其中CEONOS NVM单元需要两个或三个附加掩模，但是基本上使用用于形成的相同的标准CMOS流程 NMOS晶体管。 该单元类似于NMOS单元，但是包括替代标准NMOS栅极氧化物并用于存储NVM数据的氧化物 - 氮化物 - 氧化物（ONO）层。 这些电池采用特殊的源极/漏极工程，包括袋式注入和轻掺杂漏极扩展，这有助于使用低电压（例如5V）对CEONOS NVM单元进行编程/擦除。 使用相应的NMOS工艺形成多晶硅栅极，源极/漏极接触和金属化。 CEONOS NVM单元以空间有效的X阵列图案排列，使得每组四个单元共享漏极扩散和三个位线。 编程涉及标准CHE注入或脉冲搅拌界面基板热电子注入（PAISHEI）。

公开(公告)号：US11522079B2

公开(公告)日：2022-12-06

申请号：US16654977

申请日：2019-10-16

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Victor Kairys ,  Ruth Shima-edelstein

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L23/34 ,  H01L31/113 ,  H01L29/82 ,  H01L31/0304 ,  H01L31/024 ,  H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L31/18 ,  G01N27/22 ,  G01R33/02 ,  G01J1/42 ,  H01L29/20 ,  H01L21/265 ,  H01L21/285 ,  H01L21/266

Abstract: An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.

公开(公告)号：US20220018977A1

公开(公告)日：2022-01-20

申请号：US16948169

申请日：2020-09-04

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Pikhay Evgeny

IPC: G01T1/24

Abstract: A radiation sensor that may include a first transistor, a first isolated conductive structure that comprises a floating gate of the first transistor, a first group of radiation sensing diodes that are coupled to each other, wherein the first group is configured to convert sensed radiation that is sensed by the first group to a first output signal, and to change a state of the first isolated conductive structure using the first output signal, a second transistor, a second isolated conductive structure that comprises a floating gate of the second transistor, and a second group of radiation sensing diodes that are coupled to each other, wherein the second group is configured to convert sensed radiation that is sensed by the second group to a second output signal, and to change a state, under a control of the first transistor, of the second isolated conductive structure using the second output signal.

公开(公告)号：US11195933B2

公开(公告)日：2021-12-07

申请号：US16781272

申请日：2020-02-04

Applicant: Tower Semiconductor Ltd.

Inventor： Ruth Shima-Edelstein ,  Ronen Shaul ,  Roy Strul ,  Anatoly Sergienko ,  Liz Poliak ,  Ido Gilad ,  Alex Sirkis ,  Yakov Roizin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/205 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.

公开(公告)号：US10788375B2

公开(公告)日：2020-09-29

申请号：US15834505

申请日：2017-12-07

Applicant: TOWER SEMICONDUCTOR LTD.

Inventor： Yakov Roizin ,  Menachem Vofsy ,  Alexey Heiman ,  Yossi Rosenwaks ,  Klimentiy Shimanovich ,  Yhonatan Vaknin

IPC: G01K7/01 ,  H01L29/16 ,  G01N33/00 ,  H01L23/34 ,  G01K7/00 ,  G01K7/16 ,  H01L29/06 ,  H01L29/40 ,  H01L29/775

Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

公开(公告)号：US10770573B2

公开(公告)日：2020-09-08

申请号：US16136714

申请日：2018-09-20

Applicant: TOWER SEMICONDUCTOR LTD. ,  RAMOT at Tel Aviv University Ltd.

Inventor： Zohar Shaked ,  Yakov Roizin ,  Menachem Vofsy ,  Alexey Heiman ,  Yossi Rosenwaks ,  Klimentiy Shimanovich ,  Yhonatan Vaknin

IPC: H01L29/775 ,  G01N27/414 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423

Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.