公开(公告)号：US20240049462A1

公开(公告)日：2024-02-08

申请号：US17818166

申请日：2022-08-08

Applicant: Tower Semiconductor Ltd.

Inventor： Evgeny Pikhay ,  Michael Yampolsky ,  Yakov Roizin

IPC: H01L27/11521 ,  H01L27/11558 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/7885 ,  H01L29/66825

Abstract: A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source/drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source/drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and/or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program/erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.

公开(公告)号：US11231510B1

公开(公告)日：2022-01-25

申请号：US16948169

申请日：2020-09-04

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Pikhay Evgeny

IPC: G01T1/24

Abstract: A radiation sensor that may include a first transistor, a first isolated conductive structure that comprises a floating gate of the first transistor, a first group of radiation sensing diodes that are coupled to each other, wherein the first group is configured to convert sensed radiation that is sensed by the first group to a first output signal, and to change a state of the first isolated conductive structure using the first output signal, a second transistor, a second isolated conductive structure that comprises a floating gate of the second transistor, and a second group of radiation sensing diodes that are coupled to each other, wherein the second group is configured to convert sensed radiation that is sensed by the second group to a second output signal, and to change a state, under a control of the first transistor, of the second isolated conductive structure using the second output signal.

公开(公告)号：US11081613B2

公开(公告)日：2021-08-03

申请号：US16535548

申请日：2019-08-08

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Carmel Sahar ,  Victor Kairys ,  Ruth Shima-edelstein

IPC: H01L31/112 ,  G01J1/42 ,  H01L31/0304 ,  H01L31/024

Abstract: A UV sensor includes a GaN stack including a low-resistance GaN layer formed over a nucleation layer, and a high-resistance GaN layer formed over the low-resistance GaN layer, wherein a 2DEG conductive channel exists at the upper surface of the high-resistance GaN layer. An AlGaN layer is formed over the upper surface of the high-resistance GaN layer. A source contact and a drain contact extend through the AlGaN layer and contact the upper surface of the high-resistance GaN layer (and are thereby electrically coupled to the 2DEG channel). A drain depletion region extends entirely from the upper surface of the high-resistance GaN layer to the low-resistance GaN layer under the drain contact. An electrical current between the source and drain contacts is a function of UV light received by the GaN stack. An electrode is connected to the low-resistance GaN layer to allow for electrical refresh of the UV sensor.

公开(公告)号：US20190245086A1

公开(公告)日：2019-08-08

申请号：US15888071

申请日：2018-02-04

Applicant: Tower Semiconductor Ltd.

Inventor： Alexey Heiman ,  Igor Aisenberg ,  Abed Qaddah ,  Yakov Roizin

IPC: H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28

Abstract: A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.

公开(公告)号：US10083771B2

公开(公告)日：2018-09-25

申请号：US14753174

申请日：2015-06-29

Applicant: Tower Semiconductor Ltd. ,  RedCat Devices Srl

Inventor： Yakov Roizin ,  Cristiano Calligaro

IPC: G21H1/06 ,  H01L27/142 ,  G11C11/417 ,  G11C5/14 ,  H01L27/06

CPC classification number: G21H1/06 ,  G11C5/14 ,  G11C11/417 ,  H01L27/0617 ,  H01L27/142

Abstract: An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.

公开(公告)号：US20170160248A1

公开(公告)日：2017-06-08

申请号：US14958037

申请日：2015-12-03

Applicant: Tower Semiconductor Ltd.

Inventor： Yakov Roizin ,  Menachem Vofsy

IPC: G01N33/00 ,  H01L43/08 ,  G01N27/74 ,  H01L43/02

CPC classification number: G01N33/0065 ,  G01N27/74 ,  G01N33/0027 ,  G01N33/0062 ,  H01L27/22 ,  H01L43/08

Abstract: A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layer's blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ element's temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layer's magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout. In one embodiment, multiple MTJ elements connected in a NAND-type string switch at different concentration levels to provide highly accurate quantitative measurement data.

公开(公告)号：US20160286151A1

公开(公告)日：2016-09-29

申请号：US14665803

申请日：2015-03-23

Applicant: Tower Semiconductor Ltd.

Inventor： Assaf Lahav ,  Amos Fenigstein ,  Yakov Roizin ,  Avi Strum

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/376

CPC classification number: H04N5/37452 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14614 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/3765

Abstract: A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Abstract translation: 全局快门（GS）图像传感器像素包括通过第一传输门晶体管连接到存储器节点的钉扎光电二极管和通过第二传输栅极晶体管连接到存储器节点的浮动扩散。 存储节点包括设置在第一传输栅极晶体管下方的掩埋沟道部分和设置在第一和第二传输栅极晶体管之间的连续的钉扎二极管部分，其中两个存储器节点部分具有不同的掺杂水平，使得本征横向电场驱动电子 从埋入通道部分进入固定二极管部分。 浮动扩散节点类似地包括设置在第二传输栅极晶体管下方的掩埋沟道部分和连续的钉扎二极管部分，其产生将电子驱动到浮动扩散的钉扎二极管部分的第二本征横向电场。 公开了一种有助于低噪声CDS读出的6T CMOS像素。

公开(公告)号：US20160133666A1

公开(公告)日：2016-05-12

申请号：US14536649

申请日：2014-11-09

Applicant: Tower Semiconductor Ltd.

Inventor： Amos Fenigstein ,  Yakov Roizin ,  Avi Strum

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/1462 ,  H01L27/14689 ,  H01L27/14692 ,  H01L27/14698

Abstract: A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO2 generated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Abstract translation: 一种制造图像传感器和其他半导体IC的方法，其控制在后端处理期间产生的氢气量。 后端处理包括在前端处理完成之后形成多个金属化层（即，在形成预金属电介质之后），其中每个金属化层包括图案化的铝结构，层间电介质（ILD）层，包括基于TEOS的 形成在图案化铝结构上的氧化物。 在至少一个ILD层上形成包含诸如硅烷氧化物（即通过硅烷CVD工艺生成的SiO 2）的低含水量氧化物的盖层。 在铝过蚀刻期间，通过将下面的ILD材料与等离子体环境隔离，盖层用作随后形成的下一个金属化层的金属层的蚀刻停止层，这显着地减少了氢的生成和迁移到前端 结构。

公开(公告)号：US20150108618A1

公开(公告)日：2015-04-23

申请号：US14398735

申请日：2013-05-07

Applicant: Ramot at Tel-Aviv University Ltd. ,  Tower Semiconductor Ltd.

Inventor： Simon Litsyn ,  Gil Rosenman ,  Amir Handelman ,  Yakov Roizin

IPC: H01L21/02 ,  C08J9/26

CPC classification number: H01L21/02203 ,  B82Y30/00 ,  B82Y40/00 ,  C08J9/26 ,  C08J2201/042 ,  C08J2205/024 ,  C08J2383/04 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02255 ,  H01L21/02282

Abstract: A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.

Abstract translation: 描述多孔层。 多孔层包括具有纳米空隙分布的固化的溶胶 - 凝胶无机材料，其中至少一些纳米空隙至少部分地由碳或含碳的疏水物质内部涂覆。

公开(公告)号：US12260922B2

公开(公告)日：2025-03-25

申请号：US18121466

申请日：2023-03-14

Applicant: TOWER PARTNERS SEMICONDUCTOR CO., LTD. ,  TOWER SEMICONDUCTOR LTD.

Inventor： Hiroshige Hirano ,  Hiroaki Kuriyama ,  Masahiko Sakagami ,  Micha Gutman ,  Erez Sarig ,  Yakov Roizin

IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.