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公开(公告)号：US20240298547A1
公开(公告)日：2024-09-05
申请号：US18122165
申请日：2023-03-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Che-Wei Chang , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu
IPC: H10N50/10 , H01L23/522 , H01L23/528 , H10B61/00 , H10N50/80
CPC classification number: H10N50/10 , H01L23/5226 , H01L23/5283 , H10B61/00 , H10N50/80
Abstract: A magnetic random access memory structure includes a first dielectric layer, a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; a mask layer surrounding the protective layer, and a spacer layer surrounding the mask layer and the protective layer.
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公开(公告)号：US20240027550A1
公开(公告)日：2024-01-25
申请号：US18376843
申请日：2023-10-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11864468B2
公开(公告)日：2024-01-02
申请号：US17348776
申请日：2021-06-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
CPC classification number: H10N50/10 , G11C11/161 , H01F10/3254 , H10B61/00 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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公开(公告)号：US20230309414A1
公开(公告)日：2023-09-28
申请号：US18202275
申请日：2023-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20220367791A1
公开(公告)日：2022-11-17
申请号：US17348776
申请日：2021-06-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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Patent Agency Ranking
公开(公告)号：US20220310902A1
公开(公告)日：2022-09-29
申请号：US17242322
申请日：2021-04-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Si-Han Tsai , Shun-Yu Huang , Chen-Yi Weng , Ju-Chun Fan , Che-Wei Chang , Yi-Yu Lin , Po-Kai Hsu , Jing-Yin Jhang , Ya-Jyuan Hung
Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
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公开(公告)号：US11139428B2
公开(公告)日：2021-10-05
申请号：US16589083
申请日：2019-09-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US09837541B1
公开(公告)日：2017-12-05
申请号：US15344602
申请日：2016-11-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Che-Wei Chang , Chun-Hsiung Wang , Chih-Wei Chen
CPC classification number: H01L29/7851 , H01L29/0653 , H01L29/66681 , H01L29/66795 , H01L29/7816
Abstract: A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.
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公开(公告)号：US12146927B2
公开(公告)日：2024-11-19
申请号：US18376451
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US20240315050A1
公开(公告)日：2024-09-19
申请号：US18676441
申请日：2024-05-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Che-Wei Chang , Ching-Hua Hsu , Chen-Yi Weng
CPC classification number: H10B61/22 , G01R33/098 , H10N50/01 , H10N50/10 , H10N50/20
Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on a substrate, forming a first trench in the IMD layer, forming a metal layer in the first trench, planarizing the metal layer to form a first metal interconnection in the IMD layer and a first recess atop the first metal interconnection, and then forming a first bottom electrode (BE) in the first recess.
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