公开(公告)号：US11424258B2

公开(公告)日：2022-08-23

申请号：US17177211

申请日：2021-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiaojuan Gao ,  Chi Ren

IPC: H01L21/00 ,  H01L27/11531 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11529

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The shape angle connects to the first concave surface.

公开(公告)号：US20210280590A1

公开(公告)日：2021-09-09

申请号：US17331319

申请日：2021-05-26

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

公开(公告)号：US11100995B2

公开(公告)日：2021-08-24

申请号：US17030124

申请日：2020-09-23

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US11056495B2

公开(公告)日：2021-07-06

申请号：US16455297

申请日：2019-06-27

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

公开(公告)号：US20240355936A1

公开(公告)日：2024-10-24

申请号：US18327081

申请日：2023-06-01

Applicant: United Microelectronics Corp.

Inventor： Boon Keat Toh ,  Chih-Hsin Chang ,  Szu Han Wu ,  Chi Ren

IPC: H01L29/788 ,  H01L29/45 ,  H01L29/66 ,  H10B41/35

CPC classification number: H01L29/788 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66825 ,  H10B41/35

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.

公开(公告)号：US12057481B2

公开(公告)日：2024-08-06

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US12040369B2

公开(公告)日：2024-07-16

申请号：US17835965

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chi Ren

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.

公开(公告)号：US11943920B2

公开(公告)日：2024-03-26

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H10B43/40

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

公开(公告)号：US11901318B2

公开(公告)日：2024-02-13

申请号：US17160400

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L23/53257 ,  H01L2224/024 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0391 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

公开(公告)号：US20230380154A1

公开(公告)日：2023-11-23

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

CPC classification number: H10B41/30 ,  H01L29/788 ,  H01L29/518 ,  H01L29/513 ,  H01L29/42328

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.