公开(公告)号：US09899523B2

公开(公告)日：2018-02-20

申请号：US14594159

申请日：2015-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  Yi-Wei Chen ,  Jhen-Cyuan Li

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

公开(公告)号：US20170358455A1

公开(公告)日：2017-12-14

申请号：US15688885

申请日：2017-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/308 ,  H01L27/088 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US09502530B2

公开(公告)日：2016-11-22

申请号：US14935441

申请日：2015-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

公开(公告)号：US09397190B2

公开(公告)日：2016-07-19

申请号：US14341838

申请日：2014-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

公开(公告)号：US20140273368A1

公开(公告)日：2014-09-18

申请号：US13802542

申请日：2013-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/8238

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US08829575B2

公开(公告)日：2014-09-09

申请号：US13727540

申请日：2012-12-26

Applicant: United Microelectronics Corp.

Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

公开(公告)号：US12300743B2

公开(公告)日：2025-05-13

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US10529856B2

公开(公告)日：2020-01-07

申请号：US16028187

申请日：2018-07-05

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US10050146B2

公开(公告)日：2018-08-14

申请号：US14462114

申请日：2014-08-18

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US09691901B2

公开(公告)日：2017-06-27

申请号：US14873214

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  I-Fan Chang ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.