公开(公告)号：US20200083344A1

公开(公告)日：2020-03-12

申请号：US16123868

申请日：2018-09-06

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/49 ,  H01L29/45

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

公开(公告)号：US20250017121A1

公开(公告)日：2025-01-09

申请号：US18449716

申请日：2023-08-15

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00

Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.

公开(公告)号：US20250008849A1

公开(公告)日：2025-01-02

申请号：US18221385

申请日：2023-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Min Ting ,  Chuan-Fu Wang ,  Yu-Huan Yeh

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode, a spacer covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode, and a top electrode capping the spacer and the resistive switching layer.

公开(公告)号：US20240407274A1

公开(公告)日：2024-12-05

申请号：US18219717

申请日：2023-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.

公开(公告)号：US20240407273A1

公开(公告)日：2024-12-05

申请号：US18218602

申请日：2023-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Hsiang-Hung Peng ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.

公开(公告)号：US20240334850A1

公开(公告)日：2024-10-03

申请号：US18741808

申请日：2024-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8833 ,  H10B63/00 ,  H10N70/023 ,  H10N70/063 ,  H10N70/841

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

公开(公告)号：US11997935B2

公开(公告)日：2024-05-28

申请号：US17953341

申请日：2022-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00

CPC classification number: H10N70/826 ,  H10N70/063 ,  H10N70/841 ,  H10N70/8833

Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.

公开(公告)号：US20240107902A1

公开(公告)日：2024-03-28

申请号：US17970560

申请日：2022-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H01L45/00 ,  H01L23/48 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L23/481 ,  H01L27/24 ,  H01L45/1666

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

公开(公告)号：US11864473B2

公开(公告)日：2024-01-02

申请号：US17404934

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: G11C11/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/8833

Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

公开(公告)号：US11778830B2

公开(公告)日：2023-10-03

申请号：US17979789

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

CPC classification number: H10B43/30 ,  H10B41/10 ,  H10B41/30 ,  H10B43/10

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.