公开(公告)号：US20150137176A1

公开(公告)日：2015-05-21

申请号：US14083551

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

IPC: H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。

公开(公告)号：US20140367805A1

公开(公告)日：2014-12-18

申请号：US13917655

申请日：2013-06-14

Applicant: United Microelectronics Corp.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81C1/00

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。

公开(公告)号：US12274087B2

公开(公告)日：2025-04-08

申请号：US17990763

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Chung-Yi Chiu

IPC: H10D62/80 ,  H10D30/01 ,  H10D30/60 ,  H10D62/13 ,  H10D62/17 ,  H10D62/83 ,  H10D64/27

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

公开(公告)号：US20250098272A1

公开(公告)日：2025-03-20

申请号：US18969191

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20250054883A1

公开(公告)日：2025-02-13

申请号：US18244320

申请日：2023-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L23/64 ,  H01L23/498

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

公开(公告)号：US20240213304A1

公开(公告)日：2024-06-27

申请号：US18107521

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L27/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0647

Abstract: An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

公开(公告)号：US20230402288A1

公开(公告)日：2023-12-14

申请号：US17857158

申请日：2022-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31111 ,  H01L21/76802 ,  H01L21/31144

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

公开(公告)号：US20230369436A1

公开(公告)日：2023-11-16

申请号：US17837054

申请日：2022-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.

公开(公告)号：US20230369435A1

公开(公告)日：2023-11-16

申请号：US17835956

申请日：2022-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/401 ,  H01L21/28575 ,  H01L29/66462

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.

公开(公告)号：US11665913B2

公开(公告)日：2023-05-30

申请号：US17541226

申请日：2021-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Yu Lin ,  Po-Kai Hsu ,  Chung-Yi Chiu

IPC: H10B63/00

CPC classification number: H10B63/30 ,  H10N70/041 ,  H10N70/066 ,  H10N70/24 ,  H10N70/826

Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.