公开(公告)号：US11929431B2

公开(公告)日：2024-03-12

申请号：US18138145

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

公开(公告)号：US20230099443A1

公开(公告)日：2023-03-30

申请号：US17505663

申请日：2021-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hon-Huei Liu ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L27/11507

Abstract: The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.

公开(公告)号：US10431497B1

公开(公告)日：2019-10-01

申请号：US15951192

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/321 ,  H01L21/28

Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

公开(公告)号：US10263095B2

公开(公告)日：2019-04-16

申请号：US15995083

申请日：2018-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.

公开(公告)号：US20180108656A1

公开(公告)日：2018-04-19

申请号：US15347797

申请日：2016-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

Abstract: An asymmetrical fin structure includes a substrate. The substrate includes a top surface. A fin element extends from the substrate and connects to the substrate. The fin element includes two sidewalls respectively disposed at two opposite sides of the fin element. The sidewalls contact the top surface of the substrate. An epitaxial layer contacts and only covers one of the sidewalls. The other sidewall on the fin element does not contact any epitaxial layer.

公开(公告)号：US09859148B2

公开(公告)日：2018-01-02

申请号：US15610574

申请日：2017-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

公开(公告)号：US09831133B2

公开(公告)日：2017-11-28

申请号：US15352605

申请日：2016-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

公开(公告)号：US09786662B1

公开(公告)日：2017-10-10

申请号：US15226906

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Yu-Hsiang Hung

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate pattern is formed on the substrate, a first spacer is formed around the first gate pattern, part of the first gate pattern is removed to form a first slot, a first dielectric layer is formed into the first slot, and a replacement metal gate (RMG) process is performed to transform part of the first gate pattern into a metal gate.

公开(公告)号：US09704737B2

公开(公告)日：2017-07-11

申请号：US14816081

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

公开(公告)号：US20170062282A1

公开(公告)日：2017-03-02

申请号：US15352605

申请日：2016-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了包括多个隔离结构的基板。 第一nFET器件和第二nFET器件形成在衬底上。 第一nFET器件包括第一栅极沟槽，第二nFET包括第二栅极沟槽。 在第一栅极沟槽中形成第三底部阻挡层，同时在第二栅极沟槽中形成第三p功函数金属层。 第三底部阻挡层和第三p功函数金属层包括相同的材料。 在第一栅极沟槽和第二栅极沟槽中形成n功函数金属层。 第一栅极沟槽中的n功函数金属层直接接触第三底部势垒层，并且第二栅极沟槽中的n功函数金属层直接接触第三p功函数金属层。