公开(公告)号：US11450670B1

公开(公告)日：2022-09-20

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US20210296286A1

公开(公告)日：2021-09-23

申请号：US16848848

申请日：2020-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Yu Shen ,  Tsung-Hsun Wu ,  Liang-Wei Chiu ,  Shih-Hao Liang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/535 ,  H01L21/8234 ,  H01L25/00

Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

公开(公告)号：US10971502B2

公开(公告)日：2021-04-06

申请号：US16297722

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hui Huang ,  Tsung-Hsun Wu ,  Po-Lin Chen

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/412

Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

公开(公告)号：US20200258891A1

公开(公告)日：2020-08-13

申请号：US16297722

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hui Huang ,  Tsung-Hsun Wu ,  Po-Lin Chen

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/412

Abstract: An SRAM structure includes a substrate. A first active region, a second active region, a third active region and a fourth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

公开(公告)号：US10157662B1

公开(公告)日：2018-12-18

申请号：US15694841

申请日：2017-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Siou Wu ,  Tsung-Hsun Wu

IPC: G11C11/00 ,  G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: The present invention provides a memory cell. The memory cell includes a static random access memory (SRAM) cell located on a substrate. The SRAM cell includes a first storage node. At least one tunneling field-effect transistor (TFET), the gate of the tunneling field-effect transistor is electrically connected to the first storage node of the SRAM cell. A read bit line (RBL) electrically connected the drain of the TFET. A read terminal which is connected to a read port voltage (Vrp) and electrically connects to a source of the TFET.