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公开(公告)号:US12041784B2
公开(公告)日:2024-07-16
申请号:US17491509
申请日:2021-09-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Shih-Hung Tsai , Hon-Huei Liu , Chun-Hsien Lin
CPC classification number: H10B53/30 , H01L27/1207 , H01L27/13
Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.
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公开(公告)号:US11450747B2
公开(公告)日:2022-09-20
申请号:US17218112
申请日:2021-03-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsiao-Pang Chou , Hon-Huei Liu , Ming-Chang Lu , Chin-Fu Lin , Yu-Cheng Tung
IPC: H01L29/04 , H01L29/20 , H01L21/02 , H01L29/06 , H01L21/308 , H01L21/306 , H01L23/00 , H01L33/00 , H01L33/12 , H01L33/16 , H01L29/165
Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.
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公开(公告)号:US10692777B2
公开(公告)日:2020-06-23
申请号:US16053737
申请日:2018-08-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Shih-Hung Tsai , Chao-Hung Lin , Hon-Huei Liu , Shih-Fang Hong , Jyh-Shyang Jenq
IPC: H01L21/8238 , H01L21/225 , H01L21/324 , H01L27/092 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
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公开(公告)号:US20180342426A1
公开(公告)日:2018-11-29
申请号:US16053737
申请日:2018-08-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Shih-Hung Tsai , Chao-Hung Lin , Hon-Huei Liu , Shih-Fang Hong , Jyh-Shyang Jenq
IPC: H01L21/8238 , H01L29/78 , H01L29/66 , H01L27/092 , H01L21/225 , H01L21/324
CPC classification number: H01L21/823821 , H01L21/2255 , H01L21/2256 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0924 , H01L29/66803 , H01L29/7851
Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
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公开(公告)号:US20180218917A1
公开(公告)日:2018-08-02
申请号:US15423544
申请日:2017-02-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: En-Chiuan Liou , Hon-Huei Liu , Chia-Hung Lin , Yu-Cheng Tung
IPC: H01L21/311 , H01L21/033 , H01L21/66
Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.
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公开(公告)号:US20170033015A1
公开(公告)日:2017-02-02
申请号:US15293292
申请日:2016-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Shih-Hung Tsai , Hon-Huei Liu , Chao-Hung Lin , Nan-Yuan Huang , Jyh-Shyang Jenq
IPC: H01L21/8234 , H01L29/423 , H01L21/308 , H01L27/088
CPC classification number: H01L21/823431 , H01L21/308 , H01L21/76224 , H01L21/823481 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L29/0649 , H01L29/165 , H01L29/42372 , H01L29/7842 , H01L29/785
Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.
Abstract translation: 本发明提供一种半导体结构的形成方法,其特征在于,首先,设置具有第一鳍结构和设置在其上的第二鳍结构的衬底,接着,在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构,与第一隔离区相对地形成第二隔离区,并且在第一鳍结构和第二鳍结构的一侧形成至少外延层,其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构,并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面,此外,所述外延层具有阶梯状 形侧壁轮廓。
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公开(公告)号:US09508715B1
公开(公告)日:2016-11-29
申请号:US14817217
申请日:2015-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Chien-Ting Lin , Shih-Hung Tsai , Ssu-I Fu , Hon-Huei Liu , Jyh-Shyang Jenq
IPC: H01L27/088 , H01L21/8234
CPC classification number: H01L27/0886 , H01L21/823425 , H01L21/823431
Abstract: The present invention provides a semiconductor structure including a substrate, having a recess disposed thereon. Two first protruding portions are disposed on two sides of the recess respectively, an epitaxial layer is disposed in the recess, and an insulating layer is disposed on the substrate. A top portion of the first protruding portion is higher than a top surface of the insulating layer.
Abstract translation: 本发明提供一种包括基板的半导体结构,其上设置有凹部。 两个第一突出部分分别设置在凹槽的两侧,外延层设置在凹槽中,绝缘层设置在基板上。 第一突出部的顶部高于绝缘层的顶面。
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公开(公告)号:US09502252B2
公开(公告)日:2016-11-22
申请号:US14637400
申请日:2015-03-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Shih-Hung Tsai , Chao-Hung Lin , Hon-Huei Liu , Shih-Fang Hong , Jyh-Shyang Jenq
IPC: H01L21/225 , H01L21/8238 , H01L21/324 , H01L27/092
CPC classification number: H01L21/823821 , H01L21/2255 , H01L21/2256 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0924 , H01L29/66803 , H01L29/7851
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供其上具有至少一个鳍状结构的基底,其中鳍状结构包括顶部和底部; 以及围绕所述鳍状结构的底部部分形成掺杂层和第一衬垫。
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公开(公告)号:US09455194B1
公开(公告)日:2016-09-27
申请号:US14864852
申请日:2015-09-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Li-Wei Feng , Chien-Ting Lin , Shih-Hung Tsai , Ssu-I Fu , Hon-Huei Liu , Shih-Fang Hong , Chao-Hung Lin , Jyh-Shyang Jenq
IPC: H01L21/461 , H01L21/8234 , H01L21/3065 , H01L21/308
CPC classification number: H01L21/823412 , H01L21/3086 , H01L21/823431
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a material layer on the substrate; forming a plurality of first mandrels on the material layer of the first region and the second region; forming first spacers adjacent to the first mandrels; forming a hard mask on the first region; trimming the first spacers on the second region; removing the first mandrels; using the first spacers to remove part of the material layer for forming a plurality of second mandrels; forming second spacers adjacent to the second mandrels; removing the second mandrels; and using the second spacers to remove part of the substrate for forming a plurality of fin-shaped structures.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供具有限定在其上的第一区域和第二区域的衬底; 在所述基板上形成材料层; 在所述第一区域和所述第二区域的材料层上形成多个第一心轴; 形成与所述第一心轴相邻的第一间隔件; 在第一区域上形成硬掩模; 修剪第二区域上的第一间隔物; 去除第一个心轴; 使用所述第一间隔件去除用于形成多个第二心轴的所述材料层的一部分; 形成与所述第二心轴相邻的第二间隔件; 移除第二个心轴; 并且使用第二间隔件去除用于形成多个鳍状结构的基板的一部分。
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公开(公告)号:US20160247678A1
公开(公告)日:2016-08-25
申请号:US14629491
申请日:2015-02-24
Applicant: United Microelectronics Corp.
Inventor: Li-Wei Feng , Shih-Hung Tsai , Chao-Hung Lin , Hon-Huei Liu , An-Chi Liu , Chih-Wei Wu , Jyh-Shyang Jenq , Shih-Fang Hong , En-Chiuan Liou , Ssu-I Fu , Yu-Hsiang Hung , Chih-Kai Hsu , Mei-Chen Chen , Chia-Hsun Tseng
IPC: H01L21/033 , H01L21/66
CPC classification number: H01L21/0337 , H01L21/0338 , H01L21/3083 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L22/12
Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
Abstract translation: 形成半导体结构的方法包括以下步骤。 首先,提供具有多个心轴图案的图案化的硬掩模层。 接下来,通过图案化的硬掩模在基板上形成多个第一心轴。 接下来,执行至少一个侧壁图像传送(SIT)处理。 最后,在基板上形成多个散热片,其中每个翅片具有预定的临界尺寸(CD),并且每个心轴图案具有比预定CD大5-8倍的CD。
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