公开(公告)号：US20200235121A1

公开(公告)日：2020-07-23

申请号：US16297520

申请日：2019-03-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yi Hua Liu ,  Jun Liu ,  Lu Ming Fan

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L21/02 ,  H01L29/40 ,  H01L27/11556

Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.

公开(公告)号：US20200168625A1

公开(公告)日：2020-05-28

申请号：US16231479

申请日：2018-12-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Li Hong Xiao ,  Yu Ting Zhou

IPC: H01L27/11582 ,  H01L27/11568

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.

公开(公告)号：US10651187B2

公开(公告)日：2020-05-12

申请号：US16149093

申请日：2018-10-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.

公开(公告)号：US10559592B1

公开(公告)日：2020-02-11

申请号：US16126283

申请日：2018-09-10

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3105

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a first alternating conductor/dielectric stack disposed on the substrate and a dielectric layer disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the dielectric layer. The NAND memory device includes one or more array common source contacts extending orthogonally with respect to the surface of the substrate through the first layer stack and the second layer stack, wherein at least one of the one or more array common source contacts includes a first conductive contact and a second conductive contact that is disposed over and electrically connected with the first conductive contact.

公开(公告)号：US11864367B2

公开(公告)日：2024-01-02

申请号：US17228496

申请日：2021-04-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  G11C14/00 ,  G11C16/04 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06 ,  H01L29/04 ,  H01L29/16 ,  H01L21/76 ,  H10B12/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B10/12 ,  G11C14/0018 ,  G11C16/0483 ,  H01L21/02013 ,  H01L21/2007 ,  H01L21/50 ,  H01L21/76 ,  H01L21/8221 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/04 ,  H01L29/16 ,  H10B12/02 ,  H10B12/033 ,  H10B12/05 ,  H10B12/09 ,  H10B12/31 ,  H10B12/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/08145 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/73215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US11765898B2

公开(公告)日：2023-09-19

申请号：US17119437

申请日：2020-12-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/311 ,  H01L29/10 ,  H10B43/35 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H10B43/27 ,  H01L21/02178 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/1037 ,  H10B43/35 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/40117

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

公开(公告)号：US11706920B2

公开(公告)日：2023-07-18

申请号：US17109110

申请日：2020-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Li Hong Xiao

IPC: H01L29/40 ,  H10B43/27 ,  H01L21/28 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H10B43/30 ,  H10B43/35

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole is formed in a stack structure having a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate. A portion of each one of the plurality of first layers facing a sidewall of the initial channel hole is removed to form a channel hole. A semiconductor channel structure is formed in the channel hole. The semiconductor channel structure includes a memory layer following a profile of a sidewall of the channel hole. The plurality of first layers are removed to form a plurality of tunnels. Portions of the memory layer are removed, through the tunnels, to divide the memory layer into a plurality of disconnected sub-memory portions.

公开(公告)号：US11605593B2

公开(公告)日：2023-03-14

申请号：US16727869

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/498 ,  H01L23/538 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an interposer structure vertically between the first and second semiconductor structures. The first semiconductor structure includes a plurality of logic process-compatible devices and a first bonding layer comprising a plurality of first bonding contacts. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer comprising a plurality of second bonding contacts. The interposer structure includes a first interposer bonding layer having a plurality of first interposer contacts disposed at a first side of the interposer structure, and a second interposer bonding layer having a plurality of second interposer contacts disposed at a second side opposite of the first side of the interposer structure. The first interposer contacts is conductively connected to the second interposer contacts.

公开(公告)号：US11430756B2

公开(公告)日：2022-08-30

申请号：US16996606

申请日：2020-08-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zongliang Huo ,  Jun Liu ,  Jifeng Zhu ,  Jun Chen ,  Zi Qun Hua ,  Li Hong Xiao

IPC: H01L23/52 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed above a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. The first bonding contact is made of a first indiffusible conductive material. A second device layer is formed above a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contact is in contact with the second bonding contact at a bonding interface.

公开(公告)号：US11424208B2

公开(公告)日：2022-08-23

申请号：US16727885

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.