公开(公告)号：US20140269324A1

公开(公告)日：2014-09-18

申请号：US13830432

申请日：2013-03-14

Applicant: SILICON GRAPHICS INTERNATIONAL CORP

Inventor： Joseph George Tietz ,  Gregory Michael Thorson ,  Eric C. Fromm

IPC: H04L12/803 ,  H04L12/721

CPC classification number: H04L45/28 ,  H04L45/22 ,  H04L45/70 ,  H04L47/122

Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.

Abstract translation: 自适应路由器预测可能的未来拥塞，并且能够在拥塞发生之前选择替代路由，从而避免拥塞。 自适应路由器可以使用主路由，直到它预测将发生拥塞。 自适应路由器在主网络接口上测量数据包流量，如flit volume，以预测拥塞。 自适应路由器在拖尾时间段内保持由主网络接口处理的飞行数量的拖尾和。 如果总和超过阈值，则自适应路由器假定路由将变得拥塞，并且自适应路由器能够考虑在可能的次路由上路由将来的分组，或至少当前分组。

公开(公告)号：US08838658B2

公开(公告)日：2014-09-16

申请号：US13794483

申请日：2013-03-11

Applicant: Silicon Graphics International Corp.

Inventor： Daniel Moore ,  Andrew Gilfind

IPC: G06F17/30 ,  H04L12/24 ,  H04L29/08 ,  H04L29/06

CPC classification number: G06F3/065 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/067 ,  G06F11/1448 ,  G06F11/1464 ,  G06F11/2069 ,  G06F17/30088 ,  G06F17/302 ,  G06F2201/805 ,  G06F2201/82 ,  H04L29/06 ,  H04L41/0813 ,  H04L67/1097 ,  H04L69/329

Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.

Abstract translation: 由存储区域网络连接的一组计算机系统节点包括两类节点。 第一类节点可以作为客户端或服务器，而其他节点只能是客户端。 仅客户端节点需要更少的功能，并且可以更容易地被不同的操作系统支持。 为了最小化正常操作期间传输的数据量，负责维护集群配置数据库的服务器重复地多播IP地址，其化身号码和最新的数据库生成号码。 每个节点存储该信息，并且当检测到改变时，每个节点可以请求该节点所需的数据的更新。 仅客户端节点使用服务器的IP地址连接到服务器，从客户端节点所需的集群数据库下载信息，并上传本地磁盘连接信息。

公开(公告)号：US20140250252A1

公开(公告)日：2014-09-04

申请号：US13784160

申请日：2013-03-04

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Eric C. Fromm

IPC: G06F5/06 ,  G06F13/16

CPC classification number: G06F5/065 ,  G06F13/1689

Abstract: A modular first-in first-out circuit including at least three non-addressable memory blocks forming a data pipeline is disclosed. At least two of the memory block including a data storage structure for receiving as input data from a global data bus and a control logic structure including logic for determining whether data should be added to the data storage structure from the global data bus and whether any data within the data storage structure should be transferred to the output of the memory block. The data storage structure of the at least two memory blocks includes a first data input for selectively receiving data from the global data bus and a second data input for selectively receiving data from a previous memory block in the modular first-in first-out circuit.

Abstract translation: 公开了包括形成数据流水线的至少三个不可寻址存储块的模块化先进先出电路。 所述存储块中的至少两个包括用于从全局数据总线接收作为输入数据的数据存储结构以及包括用于确定是否应将数据从全局数据总线添加到数据存储结构的逻辑的控制逻辑结构以及是否有任何数据 在数据存储结构中应该传输到内存块的输出。 所述至少两个存储器块的数据存储结构包括用于选择性地从全局数据总线接收数据的第一数据输入和用于从模块化先进先出电路中的先前存储块选择性地接收数据的第二数据输入。

公开(公告)号：US08812721B2

公开(公告)日：2014-08-19

申请号：US13705087

申请日：2012-12-04

Applicant: Silicon Graphics International Corp.

Inventor： Steven C. Miller ,  Thomas Edward McGee ,  Bruce Alan Strangfeld

IPC: G06F15/16 ,  G06F15/167 ,  H04J3/16 ,  G06F3/00 ,  G06F13/00

CPC classification number: H03M13/05 ,  G06F13/4217 ,  G06F15/16

Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

Abstract translation: 用于传送数据的系统和方法包括确定在计算机模块处是否已经接收到交易请求信用的能力，指示可以发送交易请求消息的至少一部分的交易请求信用。 该系统和方法还包括确定事务请求消息将被发送的能力，是否可以发送交易请求消息的至少一部分，并且如果可以发送交易请求消息的至少一部分 被发送。

公开(公告)号：US20140028691A1

公开(公告)日：2014-01-30

申请号：US14042659

申请日：2013-09-30

Applicant: Silicon Graphics International Corp.

Inventor： Phillip C. Keslin

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F9/5044 ,  G06F2209/509 ,  G06T15/005 ,  G06T2200/16 ,  G09G5/36 ,  G09G2370/022 ,  H04L67/42

Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing. In an embodiment of the system, the image data is compressed before being transmitted to the client. In such an embodiment, the steps of rendering, compression, and transmission can be performed asynchronously in a pipelined manner.

Abstract translation: 提供系统，方法和计算机程序产品用于计算机图形的远程呈现。 系统包括驻留在远程服务器上的图形应用程序。 图形应用程序由位于客户端的用户或进程调用。 调用的图形应用程序继续发布图形指令。 图形指令由远程渲染控制系统接收。 鉴于客户端和服务器在图形上下文和图像处理能力方面不同，远程呈现控制系统修改图形指令以适应这些差异。 经修改的图形指令被发送到产生一个或多个渲染图像的图形渲染资源。 表示渲染图像的数据被写入一个或多个帧缓冲器。 然后，远程渲染控制系统从帧缓冲器读取该图像数据。 图像数据被发送到客户端进行显示或处理。 在系统的实施例中，图像数据在被发送到客户端之前被压缩。 在这样的实施例中，渲染，压缩和传输的步骤可以以流水线方式异步地执行。

公开(公告)号：US08581917B2

公开(公告)日：2013-11-12

申请号：US13850250

申请日：2013-03-25

Applicant: Silicon Graphics International Corp.

Inventor： Phillip C. Keslin

IPC: G06T1/00 ,  G06T15/00 ,  G06F3/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F9/5044 ,  G06F2209/509 ,  G06T15/005 ,  G06T2200/16 ,  G09G5/36 ,  G09G2370/022 ,  H04L67/42

Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing. In an embodiment of the system, the image data is compressed before being transmitted to the client. In such an embodiment, the steps of rendering, compression, and transmission can be performed asynchronously in a pipelined manner.

Abstract translation: 提供系统，方法和计算机程序产品用于计算机图形的远程呈现。 系统包括驻留在远程服务器上的图形应用程序。 图形应用程序由位于客户端的用户或进程调用。 调用的图形应用程序继续发布图形指令。 图形指令由远程渲染控制系统接收。 鉴于客户端和服务器在图形上下文和图像处理能力方面不同，远程呈现控制系统修改图形指令以适应这些差异。 经修改的图形指令被发送到产生一个或多个渲染图像的图形渲染资源。 表示渲染图像的数据被写入一个或多个帧缓冲器。 然后，远程渲染控制系统从帧缓冲器读取该图像数据。 图像数据被发送到客户端进行显示或处理。 在系统的实施例中，图像数据在被发送到客户端之前被压缩。 在这样的实施例中，渲染，压缩和传输的步骤可以以流水线方式异步地执行。

公开(公告)号：US08321634B2

公开(公告)日：2012-11-27

申请号：US13084280

申请日：2011-04-11

Applicant: Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

Inventor： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC: G06F12/00

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

Abstract translation: 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US07924570B2

公开(公告)日：2011-04-12

申请号：US12726299

申请日：2010-03-17

Applicant: Jack E. Randall ,  Giovanni Coglitore

Inventor： Jack E. Randall ,  Giovanni Coglitore

IPC: H05K5/00

CPC classification number: H05K7/1492

Abstract: A computer system comprising an interface assembly configured to support one or more I/O connections. In one variation, the computer system comprises a main board housed within a chassis, a chassis connector coupled to the chassis, and one or more I/O cables coupled to the chassis connector. In another variation, the computer assembly comprises a computer rack with a plurality of connector interfaces, each of which is adapted for engaging a computer through a chassis connector with a plurality of I/O ports.

Abstract translation: 一种包括被配置为支持一个或多个I / O连接的接口组件的计算机系统。 在一个实施例中，计算机系统包括容纳在机架内的主板，耦合到机架的机架连接器以及耦合到机架连接器的一个或多个I / O电缆。 在另一变型中，计算机组件包括具有多个连接器接口的计算机机架，每个连接器接口适于通过具有多个I / O端口的机架连接器与计算机接合。

公开(公告)号：US07724513B2

公开(公告)日：2010-05-25

申请号：US11860685

申请日：2007-09-25

Applicant: Giovanni Coglitore ,  Lawrence B. Seibold ,  Jason Enos ,  Conor Malone

Inventor： Giovanni Coglitore ,  Lawrence B. Seibold ,  Jason Enos ,  Conor Malone

IPC: H05K7/20 ,  H05K5/00 ,  G06F1/20

CPC classification number: H05K7/20745 ,  H05K7/1497

Abstract: A computing system and method of operating a computing system is provided. The computer system includes: a housing comprising a shipping container having a first interior lateral wall and a second interior lateral wall; a first row of equipment provided along the first interior lateral wall with a first exhaust region between the first row of equipment and the first interior lateral wall; a second row of equipment provided along the second interior lateral wall with a second exhaust region between the second row of equipment and the second interior lateral wall; and an aisle provided between the first row of equipment and the second row of equipment; wherein said first and second rows of equipment each comprise a plurality of rack assemblies and a plurality of computers supported by the plurality of rack assemblies such that front sides of the computers face the aisle and back sides of the computers face either the first or second interior lateral walls, said front and back sides of the computers including vents enabling cooling air to pass through the computers between the aisle and the first and second exhaust regions.

Abstract translation: 提供了一种操作计算系统的计算系统和方法。 计算机系统包括：壳体，包括具有第一内侧壁和第二内侧壁的运输容器; 沿着第一内侧壁设置的第一排设备，在第一排设备和第一内侧壁之间具有第一排气区域; 第二排设备沿着第二内侧壁设置，在第二排设备和第二内侧壁之间具有第二排气区域; 以及设置在第一排设备和第二排设备之间的通道; 其中所述第一和第二排设备各自包括多个齿条组件和由所述多个齿条组件支撑的多个计算机，使得所述计算机的前侧面向所述计算机的通道并且所述计算机的后侧面向所述第一或第二内部 所述计算机的所述前侧和后侧包括通风口，其使得冷却空气能够通过所述通道与所述第一和第二排气区域之间的计算机。

公开(公告)号：US09686206B2

公开(公告)日：2017-06-20

申请号：US14265195

申请日：2014-04-29

Applicant: Silicon Graphics International Corp.

Inventor： Joseph Carl Nemeth ,  Kevan Flint Rehm

IPC: G06F15/167 ,  H04L12/925 ,  G06F9/52

CPC classification number: H04L47/722 ,  G06F9/526

Abstract: The present invention relates to a temporal base method of mutual exclusion control of a shared resource. The invention will usually be implemented by a plurality of host computers sharing a shared resource where each host computer will read a reservation memory that is associated with the shared resource. Typically a first host computer will perform and initial read of the reservation memory and when the reservation memory indicates that the shared resource is available, the first host computer will write to the reservation memory. After a time delay, the host computer will read the reservation memory again to determine whether it has won access to the resource. The first host computer may determine that it has won access to the shared resource by checking that data in the reservation memory includes an identifier corresponding to the first host computer.