公开(公告)号：US11650881B2

公开(公告)日：2023-05-16

申请号：US17207437

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

CPC classification number: G06F11/1428 ,  G06F11/1004 ,  G06F2201/85

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: determining, by a host system, that a failure affects a storage capacity of a memory sub-system, wherein the memory sub-system comprises stored data of a storage structure; instructing, by the host system, the memory sub-system to operate at a reduced capacity and to retain the stored data of the storage structure; receiving, by the host system, a set of storage units of the memory sub-system that are affected by the failure; and recovering, by the host system, data that was in the set of storage units affected by the failure.

公开(公告)号：US20180129626A1

公开(公告)日：2018-05-10

申请号：US15862801

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Matthew S. Doyle ,  Mark J. Jeanson ,  Mark O. Maxson

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F11/1428 ,  G06F13/4018 ,  G06F13/4068 ,  G06F13/4282

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

公开(公告)号：US09552271B1

公开(公告)日：2017-01-24

申请号：US14298275

申请日：2014-06-06

Applicant: Jeffery E. Fetta ,  Eric N. Anderson

Inventor： Jeffery E. Fetta ,  Eric N. Anderson

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/3013 ,  G05B19/0428 ,  G06F11/0739 ,  G06F11/0793 ,  G06F11/1425 ,  G06F11/1428 ,  G06F11/143

Abstract: A system and method for enhanced dispatch of an operationally critical system is disclosed. The method receives a minimum equipment list associated with the system including a plurality of dispatch critical applications with at least one dispatch critical application instance. A rules set determines a plurality of schedules of the dispatch critical application instances in compliance with the minimum equipment list, each schedule associates a specific processing resource with a specific dispatch critical application instance. A monitor tracks the availability of each dispatch critical application instance and, should one or more instanced become unavailable, the method implements an alternate schedule of dispatch critical application instances in accordance with the rules set and the minimum equipment list.

Abstract translation: 公开了一种用于增强操作关键系统调度的系统和方法。 该方法接收与包括具有至少一个调度关键应用实例的多个调度关键应用程序相关联的系统的最小设备列表。 规则集根据最小设备列表确定调度关键应用实例的多个调度表，每个调度将特定处理资源与特定调度关键应用实例相关联。 监视器跟踪每个调度关键应用程序实例的可用性，并且如果一个或多个实例变得不可用，该方法根据规则集和最小设备列表实现调度关键应用实例的替代调度。

公开(公告)号：US20160378460A1

公开(公告)日：2016-12-29

申请号：US14752785

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Derek T. Chiou ,  Sitaram V. Lanka ,  Adrian M. Caulfield ,  Andrew R. Putnam ,  Douglas C. Burger

IPC: G06F9/445

CPC classification number: G06F11/00 ,  G06F8/656 ,  G06F11/0709 ,  G06F11/0793 ,  G06F11/1428 ,  G06F11/3003

Abstract: Aspects extend to methods, systems, and computer program products for partially reconfiguring acceleration components. Partial reconfiguration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During partial reconfiguration, connectivity can be maintained for any other functionality at the acceleration component untouched by the partial reconfiguration. Partial reconfiguration is more efficient to deploy than full reconfiguration of an acceleration component.

Abstract translation: 方面扩展到用于部分重新配置加速组件的方法，系统和计算机程序产品。 部分重新配置可以由各种原因实现，包括解决加速组件的功能错误或更新加速组件的功能。 在部分重新配置期间，可以通过部分重新配置不改变的加速组件处的任何其他功能来维持连接性。 部分重新配置比加速组件的完全重新配置更有效。

公开(公告)号：US20160077916A1

公开(公告)日：2016-03-17

申请号：US14484125

申请日：2014-09-11

Applicant: QUALCOMM INCORPORATED

Inventor： JEFFREY DAVID SHABEL ,  PHILIP MUELLER, JR. ,  ZHURANG ZHAO ,  CARL VICTOR STREETER ,  RASHMI KULKARNI

IPC: G06F11/14 ,  G06F11/30

CPC classification number: G06F11/141 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3287 ,  G06F1/3293 ,  G06F11/1428 ,  G06F11/3062 ,  Y02D10/122 ,  Y02D10/171

Abstract: Systems and methods for external access detection and recovery in a subsystem of a system-on-a-chip (SoC) in a portable computing device (PCD) are presented. In operation, a subsystem of the SoC is operated in an internal mode independently of the SoC while the SoC is in a low power state, such as a non-functional or zero power state or mode. The subsystem comprises a processor in communication with a memory, a sensor, and a monitor module. The monitor module detects when the processor of the subsystem requests access to a component external to the subsystem. In response to this detected request, the SoC is caused to enter into a full power state or mode, and the subsystem is caused to exit the internal mode of operation.

Abstract translation: 提出了便携式计算设备（PCD）中的片上系统（SoC）的子系统中外部访问检测和恢复的系统和方法。 在操作中，SoC的子系统在独立于SoC的内部模式下操作，而SoC处于低功率状态，例如非功能或零功率状态或模式。 子系统包括与存储器，传感器和监视器模块通信的处理器。 监视器模块检测子系统的处理器何时请求访问子系统外部的组件。 响应于该检测到的请求，使SoC进入全功率状态或模式，使子系统退出内部操作模式。

公开(公告)号：US09207877B1

公开(公告)日：2015-12-08

申请号：US13435206

申请日：2012-03-30

Applicant: Larry W. McCloskey

Inventor： Larry W. McCloskey

IPC: G06F3/06 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F3/0664 ,  G06F3/0607 ,  G06F3/0685 ,  G06F3/0686 ,  G06F3/0689 ,  G06F11/0712 ,  G06F11/0757 ,  G06F11/1415 ,  G06F11/1428

Abstract: A method for operating a virtual tape emulator that receives a request to access a directory in a disk array including a set of directories. The method includes determining whether the directory is stalled, and if so, preventing access to the directory. In another embodiment, a virtual tape emulator includes a request reception module configured to receive a request to access a directory in a disk array including a set of directories. The virtual tape emulator further includes a stall determination module configured to determine whether the directory is stalled, and an access prevention module configured to prevent access to the directory if the directory is stalled.

Abstract translation: 一种用于操作虚拟磁带仿真器的方法，该虚拟磁带仿真器接收访问包括一组目录的磁盘阵列中的目录的请求。 该方法包括确定目录是否被停止，如果是，则阻止访问该目录。 在另一个实施例中，虚拟磁带仿真器包括被配置为接收访问包括一组目录的磁盘阵列中的目录的请求的请求接收模块。 虚拟磁带仿真器还包括配置成确定目录是否停止的失速确定模块，以及配置为如果目录被停止则阻止访问目录的访问防范模块。

公开(公告)号：US08949823B2

公开(公告)日：2015-02-03

申请号：US13829157

申请日：2013-03-14

Applicant: Flextronics AP, LLC

Inventor： Christopher P. Ricci

IPC: G06F9/445 ,  B60W50/00 ,  G06F11/30 ,  B60Q11/00 ,  G06F13/14 ,  G06F11/14 ,  G06F11/34 ,  G06F11/07 ,  G06F11/20 ,  H04L12/40

CPC classification number: G06F8/61 ,  B60Q11/00 ,  B60R25/01 ,  B60W50/00 ,  G06F11/0796 ,  G06F11/1428 ,  G06F11/2035 ,  G06F11/2041 ,  G06F11/3006 ,  G06F11/3051 ,  G06F11/3055 ,  G06F11/3409 ,  G06F11/349 ,  G06F13/10 ,  G06F13/14 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: The present disclosure describes a microprocessor executable installation supervisor operable to determine, for a selected computational component to be installed in the vehicle, whether the selected computational component satisfies a requirement and/or restriction associated with the selected computational component, when installed, and, when the selected computational component can satisfy the requirement and/or restriction, create a set of data structures in the selected computational component and/or a computer readable medium on board the vehicle to bind the selected computational component to the vehicle.

Abstract translation: 本公开描述了一种微处理器可执行安装监视器，其可操作以针对要安装在车辆中的所选择的计算组件确定所选择的计算组件是否满足与所选计算组件相关联的要求和/或限制，当安装时，以及何时 所选择的计算组件可以满足要求和/或限制，在所选择的计算组件中建立一组数据结构和/或车辆上的计算机可读介质以将所选择的计算组件绑定到车辆。

公开(公告)号：US08887005B2

公开(公告)日：2014-11-11

申请号：US13596489

申请日：2012-08-28

Applicant: Pantas Sutardja ,  Abhijeet P. Gole

Inventor： Pantas Sutardja ,  Abhijeet P. Gole

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/08 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F12/0868 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1428 ,  G06F11/1666 ,  G06F11/20

Abstract: Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria.

Abstract translation: 描述了与优化可替换存储卡和板载存储器的使用相关联的系统，方法和其他实施例，作为高速缓存中的数据的存储。 根据一个实施例，一种装置包括高速缓存空间管理器，其被配置为使高速缓存处理器将存储器设备的可移动存储卡的数据存储到存储器设备的板上存储器。 该装置还包括错误率监视器，其被配置为监视可移动存储卡的操作参数，并且当操作参数满足预定标准时激活高速缓存处理器以将数据从可移动存储卡存储到板载存储器。

公开(公告)号：US08711161B1

公开(公告)日：2014-04-29

申请号：US11472865

申请日：2006-06-21

Applicant: Stefan Scotzniovsky ,  Bruce Cory ,  Charles Chew-Yuen Young ,  Anthony M. Tamasi ,  James M. Van Dyke ,  John S. Montrym ,  Sean J. Treicher

Inventor： Stefan Scotzniovsky ,  Bruce Cory ,  Charles Chew-Yuen Young ,  Anthony M. Tamasi ,  James M. Van Dyke ,  John S. Montrym ,  Sean J. Treicher

IPC: G09G5/39 ,  G06T9/00 ,  G06F12/10

CPC classification number: G01R31/318544 ,  G01R31/31704 ,  G01R31/3185 ,  G06F11/1428 ,  G06F11/2035 ,  G06F11/2289 ,  G06F11/267 ,  G11C8/06 ,  G11C29/56008 ,  G11C29/82 ,  G11C2029/0409

Abstract: A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

Abstract translation: 根据基于存储器单元操作的分析和/或测试的结果确定的操作特性设置来执行存储器单元重新配置过程。 存储器电路可以包括多个存储单元和存储单元配置控制器。 存储单元存储与各种操作相关联的信息。 存储单元配置控制器协调多个存储器单元中的每个存储器单元的选择性启用和禁用，其可以在子集或组基础上进行（例如，以字长或逐行的方式启用和/或禁用存储单元）。 可以调整地址映射，使内存空间显示为与外部组件连续。 存储单元配置控制器还可以将配置信息转发到可以调整操作以补偿存储器单元配置（例如，以防止溢出）的上游和/或下游组件。

公开(公告)号：US08656216B2

公开(公告)日：2014-02-18

申请号：US13257121

申请日：2010-02-02

Applicant: Eiichiro Shigehara

Inventor： Eiichiro Shigehara

IPC: G06F11/00

CPC classification number: G06F11/1428 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/2242

Abstract: A failure diagnostic system (100) for a multicore CPU having installed therein a plurality of CPU cores (11) that is configured to be switched from a SMP mode to an AMP mode includes: load prediction means for predicting a processing load of the multicore CPU; mode switching means for switching at least one of the CPU cores (11) to the AMP mode when the processing load is less than a threshold; and failure diagnostic means for performing a failure diagnosis of the CPU core that has been switched to the AMP mode.

Abstract translation: 一种用于安装有多个CPU核心（11）的多核CPU的故障诊断系统（100），其被配置为从SMP模式切换到AMP模式包括：负载预测装置，用于预测多核CPU的处理负荷 ; 模式切换装置，用于当所述处理负载小于阈值时，将所述CPU核心（11）中的至少一个切换到所述AMP模式; 以及用于执行已经切换到AMP模式的CPU核心的故障诊断的故障诊断装置。