公开(公告)号：US20180285375A1

公开(公告)日：2018-10-04

申请号：US15666606

申请日：2017-08-02

Applicant: VMWARE, INC.

Inventor： ASIT DESAI ,  BRYAN BRANSTETTER ,  PRASANNA AlTHAL ,  PRASAD RAO JANGAM ,  MAHESH S. HIREGOUDAR ,  ROHAN PASALKAR

IPC: G06F17/30 ,  G06F12/02 ,  G06F12/1036

CPC classification number: G06F16/13 ,  G06F12/023 ,  G06F12/1036 ,  G06F16/1727 ,  G06F2212/1044 ,  G06F2212/65

Abstract: Exemplary methods, apparatuses, and systems determine whether a skip optimization process can be used to store a file in a storage space. When it is determined that the skip optimization can be performed, a file stored in the storage space can be referenced in a file metadata data structure using direct addressing of file blocks storing the file instead of through indirect addressing (e.g., pointer addresses stored in pointer blocks).

公开(公告)号：US10078597B2

公开(公告)日：2018-09-18

申请号：US14678600

申请日：2015-04-03

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： Viswanath Mohan

IPC: G06F12/10 ,  G06F12/1036

CPC classification number: G06F12/1036 ,  G06F2212/684

Abstract: A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.

公开(公告)号：US20180260337A1

公开(公告)日：2018-09-13

申请号：US15798585

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US10062137B2

公开(公告)日：2018-08-28

申请号：US15121217

申请日：2014-02-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Indrajit Roy ,  Sangman Kim ,  Vanish Talwar

IPC: G06T1/20 ,  G06F15/167 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1072 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/60

Abstract: The communication between integrated graphics processing units (GPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated GPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

公开(公告)号：US20180157601A1

公开(公告)日：2018-06-07

申请号：US15370570

申请日：2016-12-06

Applicant: ARM Limited

Inventor： Richard F. BRYANT ,  Max John BATLEY ,  Lilian Atieno HUTCHINS ,  Sujat JAMIL

IPC: G06F12/12 ,  G06F12/1036

CPC classification number: G06F12/12 ,  G06F12/1036

Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.

公开(公告)号：US09990305B2

公开(公告)日：2018-06-05

申请号：US14490902

申请日：2014-09-19

Applicant: Nir Baruch ,  Nir Atzmon ,  David W. Todd

Inventor： Nir Baruch ,  Nir Atzmon ,  David W. Todd

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1441 ,  G06F2212/657

Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

公开(公告)号：US09971705B2

公开(公告)日：2018-05-15

申请号：US15048400

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Uday Savagaonkar ,  Francis Mckeen ,  Carlos Rozas ,  Michael Goldsmith ,  Prashant Dewan

IPC: G06F12/10 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/02

CPC classification number: G06F12/109 ,  G06F12/0284 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

公开(公告)号：US20180088976A1

公开(公告)日：2018-03-29

申请号：US15278592

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Rebekah M. Leslie-Hurd ,  Carlos V. Rozas ,  Dror Caspi

IPC: G06F9/455 ,  G06F12/1045 ,  G06F12/0817

CPC classification number: G06F9/45558 ,  G06F11/34 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/121 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/602 ,  G06F21/62 ,  G06F2009/45591 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes an execution unit, communicatively coupled to an architecturally-protected memory, the execution unit comprising a logic circuit to execute a virtual machine monitor (VMM) that supports a virtual machine (VM) comprising a guest operating system (OS) and to implement an architecturally-protected execution environment, wherein the logic circuit is to responsive to executing a blocking instruction by the guest OS directed at a first page stored in the architecturally-protected memory during a first time period identified by a value stored in a first counter, copy the value from the first counter to a second counter, responsive to executing a first tracking instruction issued by the VMM, increment the value stored in the first counter, and set a flag to indicate successful execution of the second tracking instruction.

公开(公告)号：US20180060247A1

公开(公告)日：2018-03-01

申请号：US15620663

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/02 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09864680B2

公开(公告)日：2018-01-09

申请号：US15292583

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Steven M. Partlow

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1036

CPC classification number: G06F12/023 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/0223 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/1036 ,  G06F12/12 ,  G06F17/3007 ,  G06F17/30233 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/50 ,  G06F2212/657

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.