公开(公告)号：US20150325314A1

公开(公告)日：2015-11-12

申请号：US14273851

申请日：2014-05-09

Applicant: Oracle International Corporation

Inventor： Thomas A Ziaja ,  Murali M. R. Gala

IPC: G11C29/12 ,  G11C7/10

CPC classification number: G11C29/32 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C29/12 ,  G11C29/12015 ,  G11C2207/007

Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.

Abstract translation: 公开了一种用于对集成电路（IC）中的存储器阵列进行高速测试的方法和装置。 在一个实施例中，IC包括存储器阵列和耦合以将输入信号提供到存储器阵列中的多个输入电路。 多个输入电路中的每一个包括具有耦合到存储器阵列的对应输入的数据输出的输入触发器，选择电路被配置为选择到输入触发器的数据输入的数据路径和数据路径移位 寄存器耦合以控制提供给选择电路的选择信号的状态，其中数据路径移位寄存器包括多个多路复用器。 当在测试模式下操作IC时，多个输入电路被配置为以IC的工作时钟速度向存储器阵列提供输入信号。

公开(公告)号：US20150287443A1

公开(公告)日：2015-10-08

申请号：US14744655

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Gopalkrishna Ullal Nayak ,  Matthew Craig Bullock

IPC: G11C7/10 ,  G11C29/04

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C29/04 ,  H01L22/14 ,  H01L22/20

Abstract: In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.

Abstract translation: 在用于电子设备的半导体芯片中，可编程修剪代码与默认修剪代码无关。 通过选择默认修剪代码或可编程修剪代码来生成输出修剪代码。 通过在至少一个半导体芯片的制造期间通过在金属互连层中根据第一金属布局形成金属互连来设定多个半导体芯片的默认修剪代码。 通过在后续半导体芯片的制造期间通过在金属互连层中根据第二金属布局形成金属互连来复位默认修剪代码。

公开(公告)号：US20150221384A1

公开(公告)日：2015-08-06

申请号：US14686092

申请日：2015-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicholas Hendrickson

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

Abstract translation: 操作存储器件的方法包括将增加的感测电压施加到多个存储器单元，其中多个存储器单元中的存储单元每个存储表示两位或多位数据的数据状态。 所述方法还包括响应于增加的感测电压达到特定水平，启动对多个存储器单元中的每个存储单元的特定数据数据的数据值的传送，同时继续将增加的感测电压施加到多个存储单元 的记忆细胞。

公开(公告)号：US20150162103A1

公开(公告)日：2015-06-11

申请号：US14623133

申请日：2015-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-MIN OH ,  HO-YONG SONG ,  SEONG-JIN JANG

IPC: G11C29/00 ,  G11C8/04 ,  G11C17/16

CPC classification number: G11C29/86 ,  G11C7/1036 ,  G11C7/1051 ,  G11C8/04 ,  G11C11/4093 ,  G11C16/20 ,  G11C17/16 ,  G11C2029/0407 ,  G11C2207/107

Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

Abstract translation: 数据加载电路包括被配置为存储非易失性数据并响应于上电操作基于所存储的非易失性数据输出串行数据信号的非易失性存储器，被配置为接收串行数据信号的解串器和 基于所接收的串行数据信号以单位周期的间隔输出多个数据位;负载控制器，被配置为生成在所述单位周期的每个间隔逐个依次激活的多个加载选择信号;以及加载存储器单元 被配置为响应于所述加载选择信号在所述单位周期的每个间隔顺序地存储所述数据位。

公开(公告)号：US09019785B2

公开(公告)日：2015-04-28

申请号：US14031432

申请日：2013-09-19

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/10

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Abstract translation: 本公开包括与数据移位相关的装置和方法。 示例性设备包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移动阵列中的数据，而不经由阵列的输入/输出线传送数据。

公开(公告)号：US20150078108A1

公开(公告)日：2015-03-19

申请号：US14031432

申请日：2013-09-19

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/10

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Abstract translation: 本公开包括与数据移位相关的装置和方法。 示例性设备包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移动阵列中的数据，而不经由阵列的输入/输出线传送数据。

公开(公告)号：US20150039840A1

公开(公告)日：2015-02-05

申请号：US13959428

申请日：2013-08-05

Applicant: III Holdings 2, LLC

Inventor： Prashant R. Chandra ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Niall Joseph Dalton

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/54 ,  G06F12/0223 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/17375 ,  G11C7/1036 ,  G11C7/1072 ,  G11C21/00 ,  Y02D10/14

Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.

Abstract translation: 数据处理节点具有节点间消息传递模块，其包括多个寄存器组，每组寄存器定义GET / PUT上下文的实例和多个数据处理核心，每个数据处理核心耦合到节点间消息传递模块。 每个数据处理核心包括映射功能，用于将多个用户级过程中的每一个映射到寄存器组中的不同的一个，从而映射到相应的GET / PUT上下文实例。 将每个用户级进程映射到不同的一组寄存器使得特定的一个用户级进程能够利用其相应的GET / PUT上下文实例来执行GET / PUT动作到不同的环形缓冲区 数据处理节点通过结构耦合到数据处理节点，而不涉及任何一个数据处理核心的操作系统。

公开(公告)号：US20140310453A1

公开(公告)日：2014-10-16

申请号：US14349678

申请日：2011-10-27

Applicant: Wojciech Golab ,  Matthew D. Picket ,  Alan H. Karp

Inventor： Wojciech Golab ,  Matthew D. Picket ,  Alan H. Karp

IPC: G11C7/10 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F5/00 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/544 ,  G06F15/7821 ,  G06F2209/521 ,  G11C19/188 ,  G11C19/287

Abstract: A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Abstract translation: 支持原子操作的可移动存储器在原子操作期间使用内置的移位能力来将数据的连续子集从存储器中的第一位置移动到第二位置。 可移动存储器包括用于存储数据的存储器。 内存具有内置的移动功能。 可移位存储器还包括在存储器上定义以在连续子集上操作的原子原语。

公开(公告)号：US20140304467A1

公开(公告)日：2014-10-09

申请号：US14349352

申请日：2011-10-27

Applicant: Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro

Inventor： Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro

IPC: G11C7/10 ,  G06F5/08

CPC classification number: G06F5/08 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/28 ,  G11C21/00

Abstract: Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Abstract translation: 可移动存储器使用振铃寄存器来移位存储在可移位存储器内的环形寄存器中的数据字的连续子集。 可移位存储器包括具有内置字级移位能力的存储器。 存储器包括多个用于存储数据字的环形寄存器。 数据字的连续子集可在存储器内的第一位置到第二位置的多个环形寄存器的集合之间移位。 数据字的连续子集具有小于存储器总大小的大小。 当连续子集移位时，存储器仅移动存储在连续子集内的数据字。

公开(公告)号：US08693231B2

公开(公告)日：2014-04-08

申请号：US13495287

申请日：2012-06-13

Applicant: Akira Goda ,  Seiichi Aritome

Inventor： Akira Goda ,  Seiichi Aritome

IPC: G11C5/06

CPC classification number: G11C7/02 ,  G11C7/1036 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

Abstract: A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.

Abstract translation: 存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件 第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。 感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。