公开(公告)号：US20110068472A1

公开(公告)日：2011-03-24

申请号：US12956333

申请日：2010-11-30

Applicant: Mari AMANO ,  Munehiro TADA ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

Inventor： Mari AMANO ,  Munehiro TADA ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L23/52

CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

Abstract translation: 在形成于半导体衬底顶部的绝缘膜上形成沟槽，并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后，在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜，其中绝对值 的标准形成能量大于形成阻挡金属膜的能量，并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件，其中 增加了铜界面对阻挡金属膜的附着力，抑制了界面的铜扩散，防止了电迁移和应力迁移。

公开(公告)号：US20110034028A1

公开(公告)日：2011-02-10

申请号：US12906434

申请日：2010-10-18

Applicant: Chang Soo PARK

Inventor： Chang Soo PARK

IPC: H01L21/3205 ,  H01L21/31

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76835 ,  H01L2221/1036 ,  H01L2221/1047

Abstract: The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.

Abstract translation: 本发明涉及半导体器件的制造方法。 更具体地，该方法描述了如何制造具有形成在金属线之间的多孔，低介电常数层的半导体器件，其包括绝缘层包封填料。

公开(公告)号：US07755169B2

公开(公告)日：2010-07-13

申请号：US12357919

申请日：2009-01-22

Applicant: Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC: H01L23/544

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Abstract translation: 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：US07732294B2

公开(公告)日：2010-06-08

申请号：US12170464

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract translation: 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US20090263965A1

公开(公告)日：2009-10-22

申请号：US12408473

申请日：2009-03-20

Applicant: Roy G. GORDON ,  Hoon KIM

Inventor： Roy G. GORDON ,  Hoon KIM

IPC: H01L21/768

CPC classification number: H01L21/76864 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract translation: 用于集成电路的互连结构包括在集成电路中完全包围铜线的硅酸锰和锰氮化硅层，以及用于制造其的方法。 硅酸锰形成阻止铜从电线扩散的屏障，从而保护绝缘体不被过早击穿，并保护晶体管免受铜的退化。 硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。 铜锰硅酸盐和锰氮化硅界面的强粘附性也可防止在使用设备期间铜的电迁移而导致故障。 含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。

公开(公告)号：US20090142922A1

公开(公告)日：2009-06-04

申请号：US12262915

申请日：2008-10-31

Applicant: Seung Hyun KIM

Inventor： Seung Hyun KIM

IPC: H01L21/4763

CPC classification number: H01L21/76877 ,  H01L2221/1036 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole are formed by etching the dielectric layer so that the upper surface of the transistor is exposed. Then, a contact is formed by embedding a first conductive layer in the contact hole. Next, an etching stop layer is selectively forming on an upper part of the contact. Then, the semiconductor device is blanket-etched such that the first conductive layer remains in the trench. Next, the etching stop layer is removed. Finally, a metal line is formed by embedding a second conductive layer in the trench.

Abstract translation: 一种半导体器件的制造方法。 在一个示例性实施例中，制造半导体器件的方法包括各种步骤。 首先，在包括晶体管的上表面的半导体衬底的整个表面上形成电介质层。 接下来，通过蚀刻电介质层形成沟槽和接触孔，使晶体管的上表面露出。 然后，通过在接触孔中嵌入第一导电层形成接触。 接下来，在接触件的上部选择性地形成蚀刻停止层。 然后，半导体器件被覆盖蚀刻，使得第一导电层保留在沟槽中。 接下来，去除蚀刻停止层。 最后，通过在沟槽中嵌入第二导电层形成金属线。

公开(公告)号：US20090093100A1

公开(公告)日：2009-04-09

申请号：US11869409

申请日：2007-10-09

Applicant: Li-Qun Xia ,  Huiwen Xu ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Derek R. Witty ,  Hichem M'Saad

Inventor： Li-Qun Xia ,  Huiwen Xu ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Derek R. Witty ,  Hichem M'Saad

IPC: H01L21/76

CPC classification number: H01L21/76831 ,  C23C16/325 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885 ,  H01L2221/1036

Abstract: The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in the first dielectric layer, depositing a conformal dielectric barrier film in the trenches, wherein the conformal dielectric barrier film comprises a low k dielectric material configured to serve as a barrier against a wet etching chemistry used in forming the air gaps in the first dielectric layer, depositing a metallic diffusion barrier film over the conformal low k dielectric layer, and depositing a conductive material to fill the trenches.

Abstract translation: 本发明通常提供一种用于形成多层互连结构的方法，包括包括气隙的多层互连结构。 一个实施例提供了一种用于在半导体结构中形成导线的方法，包括在第一介电层中形成沟槽，其中在第一介电层中形成气隙，在沟槽中沉积共形介电阻挡膜，其中保形介电阻挡层 薄膜包括低k电介质材料，其被配置为用作抵抗用于形成第一介电层中的气隙的湿蚀刻化学物质的阻挡层，在保形低k电介质层上沉积金属扩散阻挡膜，并将导电材料沉积到 填补沟渠。

公开(公告)号：US07498659B2

公开(公告)日：2009-03-03

申请号：US11352273

申请日：2006-02-13

Applicant: Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC: H01L23/544

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Abstract translation: 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：US07119008B2

公开(公告)日：2006-10-10

申请号：US10380848

申请日：2001-09-18

Applicant: Hui Wang

Inventor： Hui Wang

IPC: H01L21/4763

CPC classification number: H01L21/76835 ,  C25F3/02 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/7684 ,  H01L2221/1036

Abstract: In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

Abstract translation: 在形成半导体晶片的层时，在半导体晶片上沉积电介质层。 电介质层包括具有低介电常数的材料。 凹陷区域和非凹陷区域形成在电介质层中。 金属层沉积在电介质层上以填充凹陷区域并覆盖非凹陷区域。 然后电镀金属层以除去覆盖非凹陷区域的金属层，同时将金属层保持在凹陷区域中。

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

Applicant: Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

Inventor： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC: C23F1/00

CPC classification number: H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Abstract translation: 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。