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    METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO
    21.
    发明申请
    METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO 有权
    具有低剥离比率的DRAM电容器的方法和装置

    公开(公告)号：US20130207233A1

    公开(公告)日：2013-08-15

    申请号：US13851466

    申请日：2013-03-27

    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

    Inventor： Cheng Yang ,  Bo Tao ,  Jason Luo ,  Jinganag Wu

    IPC: H01L49/02

    CPC classification number: H01L28/84 ,  H01L28/82

    Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.

    Abstract translation: 一种制造具有低耗尽率电容器的半导体集成电路器件的方法，包括：在多晶硅上形成半球状晶粒（HSG）; 在磷化氢气体中掺杂半球形多晶硅; 并在850℃下快速热氧化掺杂的半球晶粒状多晶硅10秒。 该方法还包括将快速热氧化的半球状多晶硅氮化并在氮化硅层上沉积氧化铝膜。 提供了根据所公开的制造方法具有低耗尽率电容器的半导体集成电路器件。

    Method and device for a DRAM capacitor having low depletion ratio
    22.
    发明授权
    Method and device for a DRAM capacitor having low depletion ratio 有权
    具有低耗尽率的DRAM电容器的方法和装置

    公开(公告)号：US08426286B2

    公开(公告)日：2013-04-23

    申请号：US13078917

    申请日：2011-04-01

    Applicant: Cheng Yang ,  Bo Tao ,  Jason Luo ,  Jingang Wu

    Inventor： Cheng Yang ,  Bo Tao ,  Jason Luo ,  Jingang Wu

    IPC: H01L21/20

    CPC classification number: H01L28/84 ,  H01L28/82

    Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.

    Abstract translation: 一种制造具有低耗尽率电容器的半导体集成电路器件的方法，包括：在多晶硅上形成半球状晶粒（HSG）; 在磷化氢气体中掺杂半球形多晶硅; 并在850℃下快速热氧化掺杂的半球晶粒状多晶硅10秒。 该方法还包括将快速热氧化的半球状多晶硅氮化并在氮化硅层上沉积氧化铝膜。 提供了根据所公开的制造方法具有低耗尽率电容器的半导体集成电路器件。

    Electronic device having electrode with high area density and improved mechanical stability
    25.
    发明授权
    Electronic device having electrode with high area density and improved mechanical stability 有权
    具有电极面积密度高，机械稳定性好的电子器件

    公开(公告)号：US08283750B2

    公开(公告)日：2012-10-09

    申请号：US12299325

    申请日：2007-04-30

    Applicant: Lionel Guiraud ,  Francois Lecornec ,  Johan H. Klootwijk ,  Freddy Roozeboom ,  David D. R. Chevrie

    Inventor： Lionel Guiraud ,  Francois Lecornec ,  Johan H. Klootwijk ,  Freddy Roozeboom ,  David D. R. Chevrie

    IPC: H01L29/00

    CPC classification number: H01L27/0805 ,  H01L27/10817 ,  H01L27/10829 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/82 ,  H01L28/90 ,  H01L29/6609 ,  H01L29/66181 ,  H01L29/861

    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

    Abstract translation: 本发明涉及一种包括电气元件的电气设备，电气元件包括具有第一表面（106）和柱（108）的第一电极（104），该柱从第一表面沿第一方向（110）延伸， ，所述柱具有从所述第一表面平行于所述第一方向测量的长度，所述柱具有垂直于所述第一方向的横截面（116），所述柱具有封闭所述柱并且沿所述第一方向延伸的侧壁表面（120） 其特征在于，所述支柱包括沿柱的长度的至少一部分延伸的刻痕（124）和突起（122）中的任何一个，以提供支柱（108）改善的机械稳定性。 电极允许以成本有效的方式制造诸如电容器，储能装置或二极管的电气元件，具有改进的性能。

    Methods of Manufacturing Semiconductor Devices
    27.
    发明申请
    Methods of Manufacturing Semiconductor Devices 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20110306197A1

    公开(公告)日：2011-12-15

    申请号：US13156729

    申请日：2011-06-09

    Applicant: Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

    Inventor： Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

    IPC: H01L21/3205

    CPC classification number: H01L28/82

    Abstract: Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.

    Abstract translation: 提供制造半导体器件的方法，包括在衬底上形成具有衬垫的绝缘层; 在所述绝缘层和所述焊盘上形成蚀刻停止层; 形成在所述蚀刻停止层上具有至少一个模制层的模具结构; 在模具结构上形成第一支撑层; 蚀刻第一支撑层和模具结构以形成暴露蚀刻停止层的第一开口; 在所述第一开口的侧壁上形成间隔件; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成不同于所述第一开口的第二开口，暴露所述焊盘的具有第一相关区域的第一部分; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成暴露所述焊盘的具有第二相关区域的第二部分的第三开口，所述第二相关区域大于所述第一相关区域; 并且蚀刻所述模具结构以形成宽度大于所述第三开口的宽度的第四开口。

    ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM
    28.
    发明申请
    ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 有权
    EDRAM的增强电容深度电容器

    公开(公告)号：US20110272702A1

    公开(公告)日：2011-11-10

    申请号：US12775532

    申请日：2010-05-07

    Applicant: Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    Inventor： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L28/82 ,  H01L27/10867 ,  H01L29/66181

    Abstract: A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.

    Abstract translation: 提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。 通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。 多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。 沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。 可以形成存取晶体管和其它逻辑器件。

    METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS
    30.
    发明申请
    METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS 有权
    用于半导体集成电路的氯化物化学制备纳米晶体硅材料的方法

    公开(公告)号：US20110070711A1

    公开(公告)日：2011-03-24

    申请号：US12884057

    申请日：2010-09-16

    Applicant: Mieno Fumitake

    Inventor： Mieno Fumitake

    IPC: H01L21/02 ,  H01L21/28

    CPC classification number: B82Y10/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L28/82

    Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.

    Abstract translation: 用于形成集成电路器件（例如存储器，动态随机存取存储器，闪速存储器，只读存储器，微处理器，数字信号处理器，专用集成电路）的纳米晶硅结构的方法。 该方法包括提供包括表面区域的半导体衬底。 该方法形成覆盖在表面区域上的绝缘层（例如二氧化硅，氮化硅，氮氧化硅）。 在具体实施方案中，该方法包括使用氯 - 硅烷物质形成覆盖在绝缘层上的确定厚度小于20纳米的非晶硅材料。 该方法包括对非晶硅材料进行热处理工艺以形成由非晶硅材料的厚度衍生的多于20纳米的纳米尺度的硅结构。

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