公开(公告)号：US20230187143A1

公开(公告)日：2023-06-15

申请号：US18065188

申请日：2022-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Brigitte SOULIER ,  Frédéric VOIRON ,  Jullen EL SABAHY

IPC: H01G4/33 ,  H01G4/012 ,  C25D11/18 ,  C25D11/02

CPC classification number: H01G4/33 ,  H01L28/82 ,  H01G4/012 ,  C25D11/18 ,  C25D11/022

Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.

公开(公告)号：US20230163160A1

公开(公告)日：2023-05-25

申请号：US17809727

申请日：2022-06-29

Applicant: SAMSUNG ELECTRONICS. CO., LTD.

Inventor： JUNGMIN PARK ,  HANJIN LIM ,  HYUNGSUK JUMG

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L28/75 ,  H01L27/10885 ,  H01L28/65 ,  H01L28/82

Abstract: A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

公开(公告)号：US09929086B2

公开(公告)日：2018-03-27

申请号：US15270497

申请日：2016-09-20

Applicant: Renesas Electronics Corporation

Inventor： Kazuo Tomita ,  Keiichi Yamada

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/58 ,  H01L27/02 ,  H01L23/528 ,  H01L27/01

CPC classification number: H01L23/5223 ,  H01L23/5222 ,  H01L23/5286 ,  H01L23/585 ,  H01L27/016 ,  H01L27/0248 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/82 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (D1), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D1) from each other.

公开(公告)号：US09899430B2

公开(公告)日：2018-02-20

申请号：US15089815

申请日：2016-04-04

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

Inventor： Xiaoxiang Zhang ,  Tsung Chieh Kuo ,  Zheng Liu ,  Zhichao Zhang ,  Mingxuan Liu ,  Xi Chen

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/417

CPC classification number: H01L27/1255 ,  H01L27/124 ,  H01L27/1288 ,  H01L28/82 ,  H01L28/88 ,  H01L29/41733

Abstract: Embodiments of the present disclosure provide a GOA unit and a method for producing the same and a gate driver circuit, which are directed to a field of display technique. The GOA unit includes: a TFT module and a capacitor structure formed on a substrate. The TFT module includes a gate electrode, a source electrode and a drain electrode, and the capacitor structure includes a first electrode and a second electrode configured to form a first capacitor. The gate of the TFT module is located in a same layer as the first electrode of the capacitor structure, the source electrode and the drain electrode of the TFT module are located in a same layer as the second electrode of the capacitor structure, and the second electrode has a groove. Embodiments of the present application are used for a display apparatus.

公开(公告)号：US09899372B1

公开(公告)日：2018-02-20

申请号：US15339164

申请日：2016-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Chen Zhang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L27/0629 ,  H01L21/308 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L28/82 ,  H01L28/90 ,  H01L29/785

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.

公开(公告)号：US20170309905A1

公开(公告)日：2017-10-26

申请号：US15625476

申请日：2017-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazutaka KURIKI ,  Mikio YUKAWA ,  Yuji ASANO

IPC: H01M4/38 ,  H01M12/08 ,  H01M10/0569 ,  H01G11/68 ,  H01G11/22 ,  H01G11/70 ,  H01M4/66 ,  H01M10/0525

CPC classification number: H01M4/386 ,  C30B25/005 ,  C30B29/06 ,  C30B29/62 ,  C30B33/02 ,  H01G11/06 ,  H01G11/22 ,  H01G11/26 ,  H01G11/28 ,  H01G11/30 ,  H01G11/46 ,  H01G11/50 ,  H01G11/68 ,  H01G11/70 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L28/82 ,  H01M4/0428 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/382 ,  H01M4/661 ,  H01M4/667 ,  H01M10/0525 ,  H01M10/0569 ,  H01M10/0583 ,  H01M12/08 ,  H01M2300/0037 ,  Y02E60/13 ,  Y02P70/54 ,  Y02T10/7011 ,  Y02T10/7022

Abstract: Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased,

公开(公告)号：US09722014B2

公开(公告)日：2017-08-01

申请号：US14873893

申请日：2015-10-02

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman

IPC: H01L49/02 ,  H01L27/115 ,  G11C16/10 ,  G11C16/24 ,  H01L27/11526 ,  H01L27/108

CPC classification number: H01L28/88 ,  G11C16/102 ,  G11C16/24 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L28/82

Abstract: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

公开(公告)号：US09607943B2

公开(公告)日：2017-03-28

申请号：US14736881

申请日：2015-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Christopher J. Penny ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L28/88 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53228 ,  H01L28/60 ,  H01L28/82

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

公开(公告)号：US20170040110A1

公开(公告)日：2017-02-09

申请号：US14818342

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01G4/012 ,  H01G4/30

CPC classification number: H01G4/012 ,  H01G4/306 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/82 ,  H01L28/90

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes. In another embodiment, some of the first electrodes are aligned substantially parallel to a first direction and other of the first electrodes are aligned substantially parallel to a second direction, the first and second directions being different directions.

Abstract translation: 具有至少部分地嵌入在第二电极内的第一电极的电容器结构以及制造方法。 所述方法包括例如：至少部分地在绝缘体层内提供第一电极，第一电极包括暴露部分; 用介电材料覆盖第一电极的暴露部分; 以及至少部分地围绕所述第一电极的所述电介质覆盖部分形成所述第二电极，所述第二电极通过所述电介质材料与所述第一电极物理分离。 在一个实施例中，一种方法还包括暴露第一电极的另外部分; 以及提供与第一电极的另外的暴露部分电接触的接触结构。 在另一个实施例中，一些第一电极基本上平行于第一方向排列，而另一些第一电极基本上平行于第二方向排列，第一和第二方向是不同的方向。

公开(公告)号：US09368290B2

公开(公告)日：2016-06-14

申请号：US14644632

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Eric C. Hannah ,  Rong Chen ,  John Gustafson

IPC: H01G11/26 ,  H01G11/36 ,  H01G11/86 ,  H01G9/048 ,  H01G2/02 ,  H01G11/52 ,  H01G11/54 ,  H01L49/02

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.