公开(公告)号：US07288480B2

公开(公告)日：2007-10-30

申请号：US11110918

申请日：2005-04-21

Applicant: Tetsuji Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

Inventor： Tetsuji Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

IPC: H01L21/44

CPC classification number: H01L27/1259 ,  H01L27/1214

Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer. In the second annealing, a base metal film absorbs and accumulates heat of the laser irradiation, and a semiconductor layer is supplied with heat of the base metal film in addition to heat of the laser irradiation, thereby enhancing efficiency of the silicide reaction in the source and drain regions.

Abstract translation: 对薄膜集成电路进行自对准处理，而不用担心对玻璃基板的损坏，因此可以实现电路的高速操作。 在玻璃基板上形成贱金属膜，氧化物和基底绝缘膜。 在基底绝缘膜上形成具有侧壁的TFT，并且形成覆盖TFT的金属膜。 在不会引起基板收缩的温度下由RTA等进行退火，在源极和漏极区域形成高阻金属硅化物层。 在除去未反应的金属膜之后，对第二次退火进行激光照射; 因此进行硅化物反应，高阻金属硅化物层变成低电阻金属硅化物层。 在第二退火中，贱金属膜吸收并累积激光照射的热量，并且除了激光照射的热量之外，还向半导体层供应贱金属膜的热量，从而提高源的硅化物反应的效率 和漏区。

公开(公告)号：US07282380B2

公开(公告)日：2007-10-16

申请号：US11079262

申请日：2005-03-15

Applicant: Junya Maruyama ,  Atsuo Isobe ,  Susumu Okazaki ,  Koichiro Tanaka ,  Yoshiaki Yamamoto ,  Koji Dairiki ,  Tomoko Tamura

Inventor： Junya Maruyama ,  Atsuo Isobe ,  Susumu Okazaki ,  Koichiro Tanaka ,  Yoshiaki Yamamoto ,  Koji Dairiki ,  Tomoko Tamura

IPC: H01L21/00 ,  H01L21/76

CPC classification number: H01L27/1266 ,  H01L21/6835 ,  H01L24/83 ,  H01L27/1214 ,  H01L27/1218 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

公开(公告)号：US20070120127A1

公开(公告)日：2007-05-31

申请号：US11698864

申请日：2007-01-29

Applicant: Atsuo Isobe ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Shunpei Yamazaki ,  Mai Akiba

Inventor： Atsuo Isobe ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Shunpei Yamazaki ,  Mai Akiba

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L21/02683 ,  H01L21/2022 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696

Abstract: It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed on a substrate, and a semiconductor film is formed on the insulation film. Due to this, preferentially formed is a region in the semiconductor film to be concentratedly applied by stress during crystallization with laser light. Specifically, a stripe-formed or rectangular concavo-convex is formed on the semiconductor film. Continuous-oscillation laser light is irradiated along the striped concavo-convex or along a direction of a longer or shorter axis of rectangle.

Abstract translation: 提供一种使用能够防止在TFT沟道区域中形成晶界的激光晶体化方法的半导体器件制造系统的问题，并且进一步防止由于晶界引起的TFT迁移率的明显降低，导通电流降低或截止电流增加 。 在基板上形成绝缘膜，在绝缘膜上形成半导体膜。 由此，优选形成半导体膜中通过激光在结晶期间通过应力集中施加的区域。 具体地，在半导体膜上形成条状或矩形凹凸。 连续振荡激光沿着条纹凹凸或长轴或短轴方向照射。

公开(公告)号：US20070070346A1

公开(公告)日：2007-03-29

申请号：US11600833

申请日：2006-11-17

Applicant: Atsuo Isobe ,  Shunpei Yamazaki ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Mai Akiba

Inventor： Atsuo Isobe ,  Shunpei Yamazaki ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Mai Akiba

IPC: G01J3/30

CPC classification number: H01L27/1222 ,  B23K26/0738 ,  H01L21/02354 ,  H01L21/02356 ,  H01L21/02675 ,  H01L21/02683 ,  H01L21/02686 ,  H01L21/02691 ,  H01L21/2026 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696 ,  Y10S118/90 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract translation: 提供了一种使用激光晶化方法的半导体器件制造系统，其可以避免在TFT的沟道形成区域中形成晶界，从而防止晶界大大降低TFT的迁移率，降低导通电流，并且提高截止电流 。 在绝缘膜上形成矩形或条纹图案凹陷和突出部分。 在绝缘膜上形成半导体膜。 通过沿着条形图案凹陷和绝缘膜的突出部分沿着矩形的长轴或短轴方向运行激光来对连续波激光照射半导体膜。 尽管在激光中最优选连续波激光，但也可以在照射半导体膜时使用脉冲振荡激光。

公开(公告)号：US07166863B2

公开(公告)日：2007-01-23

申请号：US10941823

申请日：2004-09-16

Applicant: Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC: H01L29/04 ,  H01L31/036

CPC classification number: H01L21/02609 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78696

Abstract: A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.

Abstract translation: 提供能够高速运行，电流驱动能力高，多个元件之间波动小的半导体元件，以及包括半导体元件的半导体器件。 半导体元件具有包括多个晶体取向的第一晶体半导体区域，而绝缘表面实际上不具有晶界，第一晶体半导体区域被设置为共同连接到包括第一晶体半导体区域的导电区域和第二晶体半导体区域 区域，其中导电区域被设​​置成跨过线性条纹图案延伸的绝缘膜。

公开(公告)号：US20060270066A1

公开(公告)日：2006-11-30

申请号：US11405514

申请日：2006-04-18

Applicant: Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

Inventor： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

IPC: H01L21/00

CPC classification number: H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

Abstract translation: 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 等离子体，其中电子密度为10〜30cm -3以上，等离子体激活时电子温度为0.2eV〜2.0eV，直接与 作为要被绝缘的栅电极的导电层的一部分。

公开(公告)号：US20060215722A1

公开(公告)日：2006-09-28

申请号：US11433670

申请日：2006-05-15

Applicant: Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

Inventor： Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

IPC: H01S5/00

CPC classification number: H01L21/02675 ,  B23K26/0604 ,  B23K26/0608 ,  B23K26/0732 ,  B23K26/0736 ,  B23K26/0738 ,  B23K26/352 ,  B23K2101/40 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/283 ,  H01L27/1285 ,  H01L27/1296 ,  H01L27/14625

Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.

公开(公告)号：US20060215721A1

公开(公告)日：2006-09-28

申请号：US11433569

申请日：2006-05-15

Applicant: Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

Inventor： Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

IPC: H01S5/00

CPC classification number: H01L21/02675 ,  B23K26/0604 ,  B23K26/0608 ,  B23K26/0732 ,  B23K26/0736 ,  B23K26/0738 ,  B23K26/352 ,  B23K2101/40 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/283 ,  H01L27/1285 ,  H01L27/1296 ,  H01L27/14625

Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.

公开(公告)号：US07078768B2

公开(公告)日：2006-07-18

申请号：US10815701

申请日：2004-04-02

Applicant: Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

Inventor： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

IPC: H01L27/12

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1277 ,  H01L29/42384

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400–700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1–5 μm wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

公开(公告)号：US20060091398A1

公开(公告)日：2006-05-04

申请号：US11256086

申请日：2005-10-24

Applicant: Mayumi Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

Inventor： Mayumi Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

IPC: H01L29/76 ,  H01L29/04

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

Abstract: It is an object of the present invention to manufacture a TFT having a small-sized LDD region in a process with a few processing step and to manufacture TFTs each having a structure depending on each circuit separately. According to the present invention, a gate electrode is a multilayer, and a hat-shaped gate electrode is formed by having the longer gate length of a lower-layer gate electrode than that of an upper-layer gate electrode. At this time, only the upper-layer gate electrode is etched by using a resist recess width to form the hat-shaped gate electrode. Accordingly, an LDD region can be formed also in a fine TFT; thus, TFTs having a structure depending on each circuit can be manufactured separately.

Abstract translation: 本发明的目的是在具有少量加工步骤的工艺中制造具有小尺寸LDD区域的TFT，并且制造各自具有依赖于每个电路的结构的TFT。 根据本发明，栅电极是多层的，并且通过使下层栅电极的栅极长度比上层栅电极的栅极长度长，形成帽形栅电极。 此时，仅通过使用抗蚀剂凹部宽度来蚀刻上层栅电极，形成帽状栅电极。 因此，也可以在精细TFT中形成LDD区域; 因此，可以分别制造具有取决于每个电路的结构的TFT。