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    Method and system for flexible network processor scheduler and data flow
    31.
    发明授权
    Method and system for flexible network processor scheduler and data flow 失效
    灵活的网络处理器调度器和数据流的方法和系统

    公开(公告)号：US07483429B2

    公开(公告)日：2009-01-27

    申请号：US11133477

    申请日：2005-05-18

    Applicant: Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

    Inventor： Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC: H04L12/56 ,  H04J3/24 ,  G06F15/00

    CPC classification number: H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

    Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

    Abstract translation: 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

    System and Method for Multicore Communication Processing
    33.
    发明申请
    System and Method for Multicore Communication Processing 有权
    多核通信处理系统与方法

    公开(公告)号：US20080181245A1

    公开(公告)日：2008-07-31

    申请号：US11669419

    申请日：2007-01-31

    Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    IPC: H04L12/56

    CPC classification number: H04L47/50

    Abstract: A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

    Abstract translation: 提供了一种用于数据处理设备之间的通信的多核处理的系统和方法。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

    Systems and methods for implementing counters in a network processor with cost effective memory
    35.
    发明授权
    Systems and methods for implementing counters in a network processor with cost effective memory 失效
    在具有成本效益的存储器的网络处理器中实现计数器的系统和方法

    公开(公告)号：US07293158B2

    公开(公告)日：2007-11-06

    申请号：US11070060

    申请日：2005-03-02

    Applicant: Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    Inventor： Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC: G06F15/00 ,  G06F12/00

    CPC classification number: H04L49/901 ,  H04L49/90

    Abstract: Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.

    Abstract translation: 公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。 实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。 网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。 实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。 每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。 在R-M-W周期的写周期期间，递增的值被写入存储器。 写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms
    36.
    发明申请
    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms 有权
    接收具有高效队列流控制，段放置和虚拟化机制的队列设备

    公开(公告)号：US20060259644A1

    公开(公告)日：2006-11-16

    申请号：US11487265

    申请日：2006-07-14

    Applicant: William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    Inventor： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    IPC: G06F15/16

    CPC classification number: H04L69/16 ,  H04L69/12 ,  H04L69/161

    Abstract: A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ. The number of entries available in the RWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ.

    Abstract translation: 一种用于卸载分裂（例如，分裂式插座，拆分式iSCSI，拆分式DAFS）堆栈环境中接收队列管理的机制，包括有效的队列流控制和TCP / IP重传支持。 上层协议（ULP）创建互联网协议套件卸载引擎（IPSOE）和ULP利用的接收工作队列和完成队列，以传输信息并执行发送操作。 当消费者开始接收操作时，接收工作队列条目（RWQE）由ULP创建并写入接收工作队列（RWQ）。 通知ISPOE对RWQ的新条目，并随后读取包含要接收的数据的指针的该条目。 接收到数据后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 在编写CQE之后，ULP随后处理该条目并将其从CQE中移除，释放了RWQ和CQ两者中的空间。 RWQ中可用的条目数由ULP监视，以便它不会覆盖任何有效的条目。 同样，IPSOE监视CQ中可用条目的数量，以免覆盖CQ。

    Systems and methods for rate-limited weighted best effort scheduling
    37.
    发明申请
    Systems and methods for rate-limited weighted best effort scheduling 失效

    公开(公告)号：US20060245443A1

    公开(公告)日：2006-11-02

    申请号：US11119329

    申请日：2005-04-29

    Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    IPC: H04L12/28 ,  G01R31/08

    CPC classification number: H04L47/623 ,  H04L47/50 ,  H04L47/568

    Abstract: Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.

    Structure and method for scheduler pipeline design for hierarchical link sharing
    40.
    发明申请
    Structure and method for scheduler pipeline design for hierarchical link sharing 失效
    用于分层链路共享的调度器流水线设计的结构和方法

    公开(公告)号：US20050177644A1

    公开(公告)日：2005-08-11

    申请号：US10772737

    申请日：2004-02-05

    Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC: G06F15/16 ,  H04L12/56

    CPC classification number: H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    Abstract translation: 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

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