公开(公告)号：US20110059580A1

公开(公告)日：2011-03-10

申请号：US12883044

申请日：2010-09-15

Applicant: Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

Inventor： Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

IPC: H01L21/50

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/40 ,  H01L23/49562 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Abstract translation: 本发明的示例性半导体管芯封装具有设置在半导体管芯的第一表面和散热部件之间的金属氧化物衬底，其具有导电裸片夹或设置在金属氧化物衬底和金属氧化物衬底之间的一个或多个电互连迹线 半导体芯片的第一表面。 散热部件可以包括散热器或适配器板，散热器可以耦合到适配器板。 导电芯片夹或电迹线为半导体管芯的第一表面提供电连接，同时金属氧化物衬底将电芯与散热部件绝缘，并提供高导热性的路径 在模具和散热部件之间。 半导体管芯的第二表面可以自由地连接到电路板，或者可以将引线框架或互连衬底附接到其上。

公开(公告)号：US07821124B2

公开(公告)日：2010-10-26

申请号：US11961589

申请日：2007-12-20

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/34 ,  H01L29/76

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract translation: 公开了半导体管芯封装及其制造方法。 示例性封装包括具有源极引线和栅极引线的引线框架，以及在引线框架的第一表面处耦合到源极和栅极引线的半导体管芯。 源极引线在引线框架的第二表面具有突出区域。 模塑材料设置在半导体管芯，栅极引线和源极引线周围，使得模具的表面和突出区域的表面被模制材料暴露。 一种示例性方法包括获得半导体管芯和引线框架，以及在引线框架和管芯的至少一部分周围形成模制材料，使得突出区域的表面通过模制材料露出。

公开(公告)号：US07800219B2

公开(公告)日：2010-09-21

申请号：US11968602

申请日：2008-01-02

Applicant: Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

Inventor： Oseob Jeon ,  Chung-Lin Wu ,  Eddy Tjhia ,  Bigildis C. Dosdos

IPC: H01L23/34 ,  H01L23/10

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/40 ,  H01L23/49562 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Abstract translation: 本发明的示例性半导体管芯封装具有设置在半导体管芯的第一表面和散热部件之间的金属氧化物衬底，其具有导电管芯夹子或设置在金属氧化物衬底和金属氧化物衬底之间的一个或多个电互连迹线 半导体芯片的第一表面。 散热部件可以包括散热器或适配器板，散热器可以耦合到适配器板。 导电芯片夹或电迹线为半导体管芯的第一表面提供电连接，同时金属氧化物衬底将电芯与散热部件绝缘，并提供高导热性的路径 在模具和散热部件之间。 半导体管芯的第二表面可以自由地连接到电路板，或者可以将引线框架或互连衬底附接到其上。

公开(公告)号：US20100123225A1

公开(公告)日：2010-05-20

申请号：US12275086

申请日：2008-11-20

Applicant: Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

Inventor： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L29/7802 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/482 ,  H01L24/16 ,  H01L24/19 ,  H01L24/31 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/00

Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Abstract translation: 公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态 抵抗性。 在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。 可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。 还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

公开(公告)号：US20080105957A1

公开(公告)日：2008-05-08

申请号：US11961589

申请日：2007-12-20

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract translation: 本发明的实施例涉及半导体管芯封装。 本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合 （c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及 源极引线结构的主表面。

公开(公告)号：US07335532B2

公开(公告)日：2008-02-26

申请号：US11560935

申请日：2006-11-17

Applicant: Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/44

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

公开(公告)号：US20070238263A1

公开(公告)日：2007-10-11

申请号：US11400731

申请日：2006-04-06

Applicant: Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

Inventor： Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

IPC: H01L21/30

CPC classification number: H01L21/76251 ,  H01L21/6835 ,  H01L24/28 ,  H01L29/78603 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.

Abstract translation: 公开了将半导体衬底接合到金属衬底的方法。 在一些实施例中，该方法包括在半导体衬底中形成半导体器件，该半导体器件包括第一表面。 该方法还包括获得金属基底。 金属基板结合到半导体器件的第一表面，其中金属基板的至少一部分形成用于半导体器件的电端子。

公开(公告)号：US20060284291A1

公开(公告)日：2006-12-21

申请号：US11448962

申请日：2006-06-06

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

公开(公告)号：US07022548B2

公开(公告)日：2006-04-04

申请号：US10744849

申请日：2003-12-22

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/48

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2924/013

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract translation: 公开了一种处理半导体衬底的方法。 该方法包括在具有导电区域的半导体衬底上提供具有孔的掩模。 掩模中的孔设置在导电区上。 将预先形成的导电柱放置在孔中并结合到导电区。

公开(公告)号：US20050206010A1

公开(公告)日：2005-09-22

申请号：US10803464

申请日：2004-03-18

Applicant: Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。