公开(公告)号：US07314828B2

公开(公告)日：2008-01-01

申请号：US11184589

申请日：2005-07-19

Applicant: Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

Inventor： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC: H01L21/4763

CPC classification number: H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

Abstract translation: 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

公开(公告)号：US07256124B2

公开(公告)日：2007-08-14

申请号：US11094011

申请日：2005-03-30

Applicant: Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

Inventor： Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

IPC: H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/76825

Abstract: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

Abstract translation: 一种制造半导体器件的方法。 首先提供在基板的顶表面上具有图案化导电层的半导体衬底。 然后形成介电层以覆盖基板。 此后，执行电子束照射程序以退火图案化导电层并降低图案化导电层的电阻。

公开(公告)号：US20070020952A1

公开(公告)日：2007-01-25

申请号：US11184589

申请日：2005-07-19

Applicant: Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

Inventor： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

Abstract translation: 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

公开(公告)号：US20060228856A1

公开(公告)日：2006-10-12

申请号：US11094011

申请日：2005-03-30

Applicant: Keng-Chu Lin ,  Yi-Chi Liao ,  H. Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

Inventor： Keng-Chu Lin ,  Yi-Chi Liao ,  H. Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

IPC: H01L21/8242

CPC classification number: H01L21/76877 ,  H01L21/76825

Abstract: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

Abstract translation: 一种制造半导体器件的方法。 首先提供在基板的顶表面上具有图案化导电层的半导体衬底。 然后形成介电层以覆盖基板。 此后，执行电子束照射程序以退火图案化导电层并降低图案化导电层的电阻。

公开(公告)号：US20060172530A1

公开(公告)日：2006-08-03

申请号：US11048215

申请日：2005-02-01

Applicant: Shwang-Ming Cheng ,  Ming Yeh ,  Tien-I Bao ,  Keng-Chu Lin

Inventor： Shwang-Ming Cheng ,  Ming Yeh ,  Tien-I Bao ,  Keng-Chu Lin

IPC: H01L21/461 ,  H01L23/52

CPC classification number: H01L21/02274 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/312 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831

Abstract: A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.

Abstract translation: 提供涉及低k电介质的半导体制造方法。 该方法包括在低k电介质的表面上沉积一般组合物C x H y Y y的烃。 烃层通过使前体材料，优选C 2 H 4 H 3或（CH 3）3 H 2， CHC 6 6 H 3 CH 3，使用PECVD法。 根据本发明的实施例，碳扩散到低k电介质中，由此降低由等离子体处理或蚀刻引起的低k电介质损伤。 其他实施例包括具有低k电介质的半导体器件，其中低k电介质具有邻近沟槽侧壁和大块电介质区域的碳调节介电区域。 在优选的实施方案中，碳调节的电介质区域的碳浓度比体电介质区域的碳浓度小约不超过约5％。

公开(公告)号：US20060003572A1

公开(公告)日：2006-01-05

申请号：US10884719

申请日：2004-07-03

Applicant: Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

Inventor： Pi-Tsung Chen ,  Keng-Chu Lin ,  Hui-Lin Chang ,  Lih-Ping Li ,  Tien-I Bao ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC: H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/3135 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.

Abstract translation: 具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

公开(公告)号：US10312107B2

公开(公告)日：2019-06-04

申请号：US13228011

申请日：2011-09-08

Applicant: Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/311 ,  H01L21/321 ,  H01L21/768

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

公开(公告)号：US09196551B2

公开(公告)日：2015-11-24

申请号：US13219317

申请日：2011-08-26

Applicant: Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract translation: 一种方法包括蚀刻晶片上的低k电介质层以在低k电介质层中形成开口。 测量晶片中有害物质的量以获得测量结果。 响应于测量结果确定用于烘烤晶片的工艺条件。 使用确定的工艺条件烘烤晶片。

公开(公告)号：US08846528B2

公开(公告)日：2014-09-30

申请号：US13306340

申请日：2011-11-29

Applicant: Joung-Wei Liou ,  Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin

Inventor： Joung-Wei Liou ,  Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin

IPC: H01L21/44

CPC classification number: H01L21/02063 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.

Abstract translation: 具有蚀刻在其上的特征和低介电常数并且由半导体衬底承载的电介质层。 蚀刻的介电层被改性，使得其表面能量通过以下至少一个来降低：（a）向该层施加热能以使层温度在100℃和400℃之间; （b）用电磁能照射该层; 和/或（c）用游离离子照射该层。

公开(公告)号：US08470708B2

公开(公告)日：2013-06-25

申请号：US12712515

申请日：2010-02-25

Applicant: Po-Cheng Shih ,  Kuan-Chen Wang ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Tai-Yen Peng ,  Wen-Kuo Hsieh ,  Chih-Hao Chen

Inventor： Po-Cheng Shih ,  Kuan-Chen Wang ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Tai-Yen Peng ,  Wen-Kuo Hsieh ,  Chih-Hao Chen

IPC: H01L21/44

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813

Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.

Abstract translation: 光刻图案的方法包括在材料层上形成掩模层并在掩模层上形成覆盖层。 覆盖层是对材料层的图案化处理的蚀刻反应性更高的含硼层。 通过使含硼层适合作为覆盖层，可以减小掩模层的厚度。 因此，也可以实现用于在材料层中形成互连金属化的更好的间隙填充。