公开(公告)号：US20050215023A1

公开(公告)日：2005-09-29

申请号：US11029221

申请日：2005-01-03

Applicant: Adam Cohen ,  Ananda Kumar ,  Michael Lockard ,  Dennis Smalley

Inventor： Adam Cohen ,  Ananda Kumar ,  Michael Lockard ,  Dennis Smalley

IPC: G01R31/02 ,  H01L21/20

CPC classification number: G01R1/06716 ,  B33Y10/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  G01R1/0483 ,  G01R1/07357 ,  G01R31/2886

Abstract: Some embodiments of the invention are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that partially coats the surface of the probe. Other embodiments are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that completely coats the surface of each layer from which the probe is formed including interlayer regions. These first two groups of embodiments incorporate both the core material and the coating material during the formation of each layer. Still other embodiments are directed to the electrochemical fabrication of microprobe arrays that are partially encapsulated by a dielectric material during a post layer formation coating process. In even further embodiments, the electrochemical fabrication of microprobes from two or more materials may occur by incorporating a coating material around each layer of the structure without locating the coating material in inter-layer regions.

公开(公告)号：US20050202660A1

公开(公告)日：2005-09-15

申请号：US10995609

申请日：2004-11-22

Applicant: Adam Cohen ,  Michael Lockard ,  Dennis Smalley ,  Marvin Kilgo

Inventor： Adam Cohen ,  Michael Lockard ,  Dennis Smalley ,  Marvin Kilgo

IPC: B81B3/00 ,  C25D1/00 ,  C25D5/02 ,  C25D5/12 ,  C25D21/12 ,  G01P15/08 ,  G01P15/125 ,  H01L21/288 ,  H01L21/48 ,  H01L21/768 ,  H01P1/202 ,  H01P3/06 ,  H01P5/18 ,  H01P11/00 ,  H05K3/24 ,  H05K3/46 ,  H01L21/425

CPC classification number: C25D1/003 ,  B81B2201/042 ,  B81C99/004 ,  G01P15/0802 ,  G01P15/125 ,  H01L21/2885 ,  H01L21/4857 ,  H01L21/76879 ,  H01P1/202 ,  H01P3/06 ,  H01P5/183 ,  H01P11/00 ,  H01P11/005 ,  H05K3/241 ,  H05K3/243 ,  H05K3/4647

Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures include operations or means for providing enhanced monitoring of build operations or detection of the results of build operations, operations or means for build problem recognition, operations or means for evaluation of corrective action options, operations or means for making corrective action decisions, and operations or means for executing actions based on those decisions.

Abstract translation: 用于生产多层结构的电化学制造工艺和设备包括用于提供构建操作的增强监控或构建操作的结果的检测，构建问题识别的操作或手段，用于评估校正动作选项的操作或手段的操作或装置 或作出纠正行动决定的手段，以及基于这些决定执行行动的操作或手段。

公开(公告)号：US20050194258A1

公开(公告)日：2005-09-08

申请号：US11029179

申请日：2005-01-03

Applicant: Adam Cohen ,  Michael Lockard ,  Kieun Kim ,  Qui Le ,  Gang Zhang ,  Uri Frodis ,  Dale McPherson ,  Dennis Smalley

Inventor： Adam Cohen ,  Michael Lockard ,  Kieun Kim ,  Qui Le ,  Gang Zhang ,  Uri Frodis ,  Dale McPherson ,  Dennis Smalley

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C25D5/02 ,  C25D5/10 ,  H01L21/44 ,  H01L21/4763

CPC classification number: C25D1/003 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/405 ,  C25D5/022 ,  C25D5/10

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

公开(公告)号：US20050176238A1

公开(公告)日：2005-08-11

申请号：US11029172

申请日：2005-01-03

Applicant: Adam Cohen ,  Michael Lockard ,  Kieun Kim ,  Qui Le ,  Gang Zhang ,  Uri Frodis ,  Dale McPherson ,  Dennis Smalley

Inventor： Adam Cohen ,  Michael Lockard ,  Kieun Kim ,  Qui Le ,  Gang Zhang ,  Uri Frodis ,  Dale McPherson ,  Dennis Smalley

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C25D5/02 ,  C25D5/10 ,  H01L21/44 ,  H01L21/4763

CPC classification number: C25D1/003 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/405 ,  C25D5/022 ,  C25D5/10

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

公开(公告)号：US20050032375A1

公开(公告)日：2005-02-10

申请号：US10841300

申请日：2004-05-07

Applicant: Michael Lockard ,  Dennis Smalley ,  Willa Larsen ,  Richard Chen

Inventor： Michael Lockard ,  Dennis Smalley ,  Willa Larsen ,  Richard Chen

IPC: B05D1/32 ,  C23C18/16 ,  C25D5/02 ,  C25D5/10 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC classification number: C25D1/003 ,  B33Y10/00 ,  C23C18/1605 ,  C23C18/1657 ,  C25D5/022 ,  C25D5/10 ,  H01L21/7682 ,  H01L21/76838

Abstract: Embodiments of the present invention provide mesoscale or microscale three-dimensional structures (e.g. components, device, and the like). Embodiments relate to one or more of (1) the formation of such structures which incorporate sheets of dielectric material and/or wherein seed layer material used to allow electrodeposition over dielectric material is removed via planarization operations; (2) the formation of such structures wherein masks used for at least some selective patterning operations are obtained through transfer plating of masking material to a surface of a substrate or previously formed layer, and/or (3) the formation of such structures wherein masks used for forming at least portions of some layers are patterned on the build surface directly from data representing the mask configuration, e.g. in some embodiments mask patterning is achieved by selectively dispensing material via a computer controlled inkjet nozzle or array or via a computer controlled extrusion device.

Abstract translation: 本发明的实施例提供中尺度或微尺寸的三维结构（例如部件，装置等）。 实施例涉及以下一个或多个（1）形成这样的结构，其结合了介电材料片和/或其中用于允许通过电介质材料的电沉积的种子层材料通过平面化操作被去除; （2）形成这样的结构，其中用于至少一些选择性图案化操作的掩模通过将掩模材料转移到衬底或先前形成的层的表面获得，和/或（3）形成这样的结构，其中掩模 用于形成至少部分一些层的图案直接来自表示掩模配置的数据在构建表面上图案化，例如 在一些实施例中，通过经由计算机控制的喷墨喷嘴或阵列或经由计算机控制的挤出装置选择性地分配材料来实现掩模图案化。

公开(公告)号：US20050032362A1

公开(公告)日：2005-02-10

申请号：US10841100

申请日：2004-05-07

Applicant: Adam Cohen ,  Dennis Smalley ,  Michael Lockard ,  Qui Le

Inventor： Adam Cohen ,  Dennis Smalley ,  Michael Lockard ,  Qui Le

IPC: C23C18/16 ,  C25D5/02 ,  C25D5/10 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/288 ,  B33Y10/00 ,  C23C18/1605 ,  C25D5/022 ,  C25D5/10 ,  H01L21/311 ,  H01L21/7682 ,  H01L21/76879

Abstract: A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first material prior to deposition of the second material. The treatment of the surface of the first material either (1) decreases the susceptibility of deposition of the second material onto the surface of the first material or (2) eases or quickens the removal of any second material deposited on the treated surface of the first material. In some embodiments the treatment of the first surface includes forming a dielectric coating over the surface and the second material is electrodeposited (e.g. using an electroplating or electrophoretic process). In other embodiments the first material is coated with a conductive material that doesn't readily accept deposits of electroplated or electroless deposited materials.

Abstract translation: 从至少第一和第二材料的多个粘附层制造三维结构的方法，其中所述第一材料是导电材料，并且其中多个层中的每一个包括在沉积之前处理第一材料的表面 的第二种材料。 第一材料的表面的处理（1）降低了将第二材料沉积到第一材料的表面上的敏感性，或（2）减轻或加快了沉积在第一材料的处理表面上的任何第二材料的去除 材料。 在一些实施例中，第一表面的处理包括在表面上形成电介质涂层，并且第二材料被电沉积（例如使用电镀或电泳工艺）。 在其它实施例中，第一材料涂覆有不容易接受电镀或无电沉积材料沉积物的导电材料。

公开(公告)号：US20080105355A1

公开(公告)日：2008-05-08

申请号：US11929597

申请日：2007-10-30

Applicant: Ananda Kumar ,  Ezekiel Kruglick ,  Adam Cohen ,  Kieun Kim ,  Gang Zhang ,  Richard Chen ,  Christopher Bang ,  Vacit Arat ,  Michael Lockard ,  Uri Frodis ,  Pavel Lembrikov ,  Jeffrey Thompson

Inventor： Ananda Kumar ,  Ezekiel Kruglick ,  Adam Cohen ,  Kieun Kim ,  Gang Zhang ,  Richard Chen ,  Christopher Bang ,  Vacit Arat ,  Michael Lockard ,  Uri Frodis ,  Pavel Lembrikov ,  Jeffrey Thompson

IPC: B32B37/00 ,  B23K31/02

CPC classification number: G01R3/00 ,  G01R1/06761 ,  G01R1/07307 ,  Y10T29/49002 ,  Y10T156/10

Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.

Abstract translation: 本发明的实施例涉及在临时衬底上形成微探针（即柔性电气或电子接触元件），切割单独的探针阵列，然后将阵列转移到空间变压器或其它永久衬底。 在将探针从其上形成探针的临时基底分离出来之前，本发明的一些实施方案将探针转移到永久性基底上，而其他实施方案相反。 一些实施例，在转移之前去除牺牲材料，而其它实施例在转移后去除牺牲材料。 一些实施例涉及使用一个或多个具有增强的纵横比（即，高度与宽度比）的焊料凸块来将第一和第二电气部件接合在一起，这是由于至少部分地由保持材料的环围绕凸块而得到的。 保留材料可以用作焊接掩模材料。

公开(公告)号：US20060053625A1

公开(公告)日：2006-03-16

申请号：US11177798

申请日：2005-07-07

Applicant: Kieun Kim ,  Adam Cohen ,  Willa Larsen ,  Richard Chen ,  Ananda Kumar ,  Ezekiel Kruglick ,  Vacit Arat ,  Gang Zhang ,  Michael Lockard ,  Christopher Bang

Inventor： Kieun Kim ,  Adam Cohen ,  Willa Larsen ,  Richard Chen ,  Ananda Kumar ,  Ezekiel Kruglick ,  Vacit Arat ,  Gang Zhang ,  Michael Lockard ,  Christopher Bang

IPC: H01R43/16 ,  H01R43/00

CPC classification number: G01R3/00 ,  C25D1/003 ,  G01R1/073 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate. Probe tip patterning may occur in a variety of different ways, including, for example, via molding in patterned holes that have been isotropically or anisotropically etched silicon, via molding in voids formed in exposed photoresist, via molding in voids in a sacrificial material that have formed as a result of the sacrificial material mushrooming over carefully sized and located regions of dielectric material, via isotropic etching of the tip material around carefully sized and placed etching shields, via hot pressing, and the like.

Abstract translation: 本发明的实施例涉及形成具有各种构造的微探针尖元件。 在一些实施例中，尖端由与探针本身相同的建筑材料形成，而在其它实施例中，尖端可以由不同的材料形成和/或可以包括涂层材料。 在一些实施例中，尖端在探针的主要部分之前形成，并且尖端形成在临时衬底附近或与临时衬底接触。 探针尖端图案化可以以各种不同的方式发生，包括例如通过在各向异性或各向异性地蚀刻硅的图案化孔中模制，通过在曝光的光致抗蚀剂中形成的空隙中模制，通过在牺牲材料中的空隙中模制， 由于牺牲材料通过电介质材料的细小尺寸和定位的区域，经由热压等等仔细地尺寸和放置的蚀刻屏蔽部分上的尖端材料的各向同性蚀刻而形成。

公开(公告)号：US20060011486A1

公开(公告)日：2006-01-19

申请号：US11139262

申请日：2005-05-26

Applicant: Michael Lockard ,  Dennis Smalley ,  Willa Larsen ,  Richard Chen

Inventor： Michael Lockard ,  Dennis Smalley ,  Willa Larsen ,  Richard Chen

IPC: B05D1/32 ,  C25D5/02

CPC classification number: C25D1/003 ,  B33Y10/00 ,  B81C1/00492 ,  C23C18/1605 ,  C25D5/022 ,  C25D5/10 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  Y10T156/10 ,  Y10T156/1041

Abstract: Embodiments of the present invention provide mesoscale or microscale three-dimensional structures (e.g. components, device, and the like). Embodiments relate to one or more of (1) the formation of such structures which incorporate sheets of dielectric material and/or wherein seed layer material used to allow electrodeposition over dielectric material is removed via planarization operations; (2) the formation of such structures wherein masks used for at least some selective patterning operations are obtained through transfer plating of masking material to a surface of a substrate or previously formed layer, and/or (3) the formation of such structures wherein masks used for forming at least portions of some layers are patterned on the build surface directly from data representing the mask configuration, e.g. in some embodiments mask patterning is achieved by selectively dispensing material via a computer controlled inkjet nozzle or array or via a computer controlled extrusion device.

公开(公告)号：US20050221529A1

公开(公告)日：2005-10-06

申请号：US11139391

申请日：2005-05-27

Applicant: Christopher Bang ,  Adam Cohen ,  Michael Lockard ,  John Evans

Inventor： Christopher Bang ,  Adam Cohen ,  Michael Lockard ,  John Evans

IPC: B81C1/00 ,  C25D1/00 ,  C25D5/02 ,  H01L21/4763 ,  H01L23/52 ,  H02N1/00

CPC classification number: H02N1/008 ,  B33Y10/00 ,  B81C1/0019 ,  C25D1/003

Abstract: Various embodiments of the invention are directed to various microdevices including sensors, actuators, valves, scanning mirrors, accelerometers, switches, and the like. In some embodiments the devices are formed via electrochemical fabrication (EFAB™).

Abstract translation: 本发明的各种实施例涉及包括传感器，致动器，阀，扫描反射镜，加速度计，开关等的各种微型装置。 在一些实施例中，通过电化学制造（EFAB TM）形成器件。