公开(公告)号：US10424526B2

公开(公告)日：2019-09-24

申请号：US15782857

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/055 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/12 ,  H01L23/488 ,  H01L23/00 ,  H01L23/16 ,  H01L21/60

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

公开(公告)号：US20190164909A1

公开(公告)日：2019-05-30

申请号：US16114251

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US10276553B2

公开(公告)日：2019-04-30

申请号：US15787712

申请日：2017-10-19

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/00 ,  H01L23/053 ,  H01L23/055 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/49 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L23/04 ,  H01L23/433

Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

公开(公告)号：US10224254B2

公开(公告)日：2019-03-05

申请号：US15497219

申请日：2017-04-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hsien-Wen Hsu ,  Yuan-Fu Lan ,  Hung-Hsin Hsu

IPC: H01L23/043 ,  H01L23/06 ,  H01L23/31 ,  H01L21/82 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

公开(公告)号：US20180301418A1

公开(公告)日：2018-10-18

申请号：US15717923

申请日：2017-09-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

Abstract: A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.

公开(公告)号：US10079218B1

公开(公告)日：2018-09-18

申请号：US15619969

申请日：2017-06-12

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang-Chien ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/19 ,  H01L21/6835 ,  H01L22/14 ,  H01L22/20 ,  H01L2221/68359 ,  H01L2224/82105

Abstract: A conductive layer is formed on a first surface of a first carrier. The redistribution layer is formed on the conductive layer. Then an open-test is performed to the redistribution layer. Since the conductive layer and the redistribution layer constitute a closed loop, a load should be presented during the open-test if the redistribution layer is formed correctly. After the open-test is performed, the first carrier and the conductive layer are removed. Then a short-test is performed to the redistribution layer. No load is presented during the short-test if the redistribution layer is formed correctly since the redistribution layer constitutes an open loop. Therefore, whether the redistribution layer has flaws can be determined before the dies are boned on the redistribution layer. Thus, no waste of the good die occurs because of the flawed redistribution layer.

公开(公告)号：US20180259558A1

公开(公告)日：2018-09-13

申请号：US15975789

申请日：2018-05-10

Applicant: Powertech Technology Inc.

Inventor： Chih-Hui Yeh ,  Ming-Jyun Yu

IPC: G01R23/02

CPC classification number: G01R23/02 ,  G01R31/2844 ,  G01R31/2879 ,  G01R31/31908 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50012 ,  G11C29/56012

Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

公开(公告)号：US20180190594A1

公开(公告)日：2018-07-05

申请号：US15717956

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/81

Abstract: A manufacturing method of a packaging structure is provided. First, a carrier is provided. A conductive layer is formed on the carrier. A conductive frame is formed on the conductive layer. The conductive frame is in contact with and electrically connected to the conductive layer. A chip is placed on the conductive layer. The conductive frame surrounds the chip. An insulation encapsulation is formed to encapsulate the chip, and the insulation encapsulation exposes an active surface of the chip. A redistribution layer is formed on the active surface of the chip. The redistribution layer extends from the active surface to the insulation encapsulation.

公开(公告)号：US09991206B1

公开(公告)日：2018-06-05

申请号：US15480323

申请日：2017-04-05

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Lien-Chia Chang ,  Chih-Ming Ko ,  Hung-Hsin Hsu

IPC: H01L23/02 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/3105 ,  H01L21/288 ,  H01L23/498 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/13

CPC classification number: H01L23/5386 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15331

Abstract: A package method includes disposing a chip and a plurality of solder bumps on a substrate by disposing a plurality of chip interfaces and the plurality of solder bumps on a plurality of first interfaces of the substrate respectively; forming a mold layer configured to encapsulate the chip and the plurality of solder bumps; grinding the mold layer to obtain a grinded mold layer and expose a top side of the chip; drilling the grinded mold layer to form a plurality of through holes corresponding to the plurality of solder bumps; and applying a conductive material to fill the plurality of through holes with the conductive material to form a plurality of electrical paths through the grinded mold layer and electrically couple to the plurality of solder bumps.

公开(公告)号：US20180114783A1

公开(公告)日：2018-04-26

申请号：US15787712

申请日：2017-10-19

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.