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    THERMAL MANAGEMENT FOR ELECTRONIC COMPONENTS
    31.
    发明公开
    THERMAL MANAGEMENT FOR ELECTRONIC COMPONENTS 审中-公开

    公开(公告)号：US20240057299A1

    公开(公告)日：2024-02-15

    申请号：US17885376

    申请日：2022-08-10

    Applicant: Seagate Technology LLC

    Inventor： Deepak Nayak ,  Hemant Mohan

    IPC: H05K7/20

    CPC classification number: H05K7/20836 ,  H05K7/20172 ,  H05K7/20718

    Abstract: A data storage system includes an enclosure, a printed circuit board positioned in the enclosure, an integrated circuit mechanically and electrically coupled to the printed circuit board, temperature sensors configured to generate temperature signals in response to measured temperatures, an air mover coupled to the enclosure and including a motor rotatable in a clockwise direction and a counterclockwise direction, and a controller configured to cause rotation of the motor in either the clockwise direction or the counterclockwise direction depending on the temperature signals.

    Magnetoresistive asymmetry compensation
    32.
    发明授权
    Magnetoresistive asymmetry compensation 有权

    公开(公告)号：US11900970B2

    公开(公告)日：2024-02-13

    申请号：US17162218

    申请日：2021-01-29

    Applicant: Seagate Technology LLC

    Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

    IPC: G11B5/09 ,  G06F13/38 ,  H03M1/12 ,  G11B5/00

    CPC classification number: G11B5/09 ,  G06F13/385 ,  H03M1/12 ,  G11B2005/0013

    Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

    Lossless namespace metadata management system
    34.
    发明授权
    Lossless namespace metadata management system 有权

    公开(公告)号：US11899952B2

    公开(公告)日：2024-02-13

    申请号：US17515021

    申请日：2021-10-29

    Applicant: Seagate Technology LLC

    Inventor： Ryan James Goss ,  David W. Claude ,  Daniel J. Benjamin ,  Thomas V. Spencer ,  Matthew B. Lovell

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.

    Opportunistic command scheduling
    35.
    发明授权
    Opportunistic command scheduling 有权

    公开(公告)号：US11893268B2

    公开(公告)日：2024-02-06

    申请号：US17579061

    申请日：2022-01-19

    Applicant: Seagate Technology LLC

    Inventor： Brian T. Edgar ,  Mark A. Gaertner

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0676

    Abstract: A method includes calculating, by a data storage device processor, at least one access trajectory from a first disc surface location to at least one second disc surface location at which at least one primary data access operation is to be carried out. The method also includes determining, by the data storage device controller, whether an opportunity to commence at least one secondary data access operation exists along or proximate to the at least one access trajectory from the first disc surface location to the at least one second disc surface location.

    METHODS OF GENE ASSEMBLY USING DNAZYMES AND USE IN DNA DATA STORAGE
    36.
    发明公开
    METHODS OF GENE ASSEMBLY USING DNAZYMES AND USE IN DNA DATA STORAGE 审中-公开

    公开(公告)号：US20240035018A1

    公开(公告)日：2024-02-01

    申请号：US17816215

    申请日：2022-07-29

    Applicant: Seagate Technology LLC

    Inventor： Gemma Roselle MENDONSA ,  Walter R. EPPLER

    IPC: C12N15/10 ,  C12N15/113

    CPC classification number: C12N15/1031 ,  C12N15/113 ,  C12N2310/127 ,  C12N2330/31 ,  G11C11/54

    Abstract: Building DNA strands at a high rate that are suitable for data storage. Methods include using DNAzyme and utilizing libraries of pre-prepared oligos. A system for the DNA strand synthesis includes: a DNA symbol library comprising a number of single strand oligo symbols; a DNA linker library comprising a first set of single strand oligo linkers and a second set of single strand oligo linkers; and a DNAzyme library comprising a number of DNAzymes. An S1 end of a first DNAzyme is adapted to join the S1 end of a symbol and an S2 end of the first DNAzyme is adapted to join an S2 end of a first linker, and an S1 end of a second DNAzyme is adapted to join an S1 end of a second linker and an S2 end of the second DNAzyme is adapted to join an S2 end of the symbol.

    On demand configuration of FPGA interfaces
    37.
    发明授权
    On demand configuration of FPGA interfaces 有权

    公开(公告)号：US11880568B2

    公开(公告)日：2024-01-23

    申请号：US17564052

    申请日：2021-12-28

    Applicant: Seagate Technology LLC

    Inventor： Rajesh Maruti Bhagwat ,  Nahoosh Hemchandra Mandlik ,  Niranjan Anant Pol ,  Hemantkumar Vitthalrao Mane

    IPC: G06F3/06

    CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

    SECURE COMMAND MEMORY BUFFER TRANSFERS IN A LOW TRUST ENVIRONMENT
    38.
    发明公开
    SECURE COMMAND MEMORY BUFFER TRANSFERS IN A LOW TRUST ENVIRONMENT 审中-公开

    公开(公告)号：US20240020050A1

    公开(公告)日：2024-01-18

    申请号：US17864900

    申请日：2022-07-14

    Applicant: Seagate Technology, LLC

    Inventor： Phillip R. Colline ,  Timothy Ted Walker ,  Steven Williams ,  Hemant Vitthalrao Mane ,  Jason Matthew Feist

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Apparatus and method for executing controller memory buffer (CMB) based data transfer commands in a distributed data processing environment. In some embodiments, a storage device having a device controller and a main non-volatile memory (NVM) is coupled to a client device via an interface. The client device respectively issues normal data transfer commands and bypass data transfer commands to the storage device. The normal data transfer commands include read and write commands that result in transfer of data between the NVM and the client device using a normal data path through the storage device. The bypass data transfer commands involve an allocated CMB of the storage device directly controlled and accessed by the client device. In this way, write data are directly placed into the CMB for writing to the NVM, and readback data from the NVM are directly recovered from the CMB by the client device.

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