公开(公告)号：US08826526B2

公开(公告)日：2014-09-09

申请号：US13281735

申请日：2011-10-26

Applicant: Shinnosuke Maeda

Inventor： Shinnosuke Maeda

IPC: H05K3/20 ,  H05K3/36 ,  H05K1/00 ,  H01L21/48 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H05K3/0026 ,  H05K2201/0358 ,  H05K2203/0228 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: A method of manufacturing a multilayer wiring substrate is provided. A foil of a metal-foil-clad resin insulation material is brought into contact with a foil of a metal-foil-clad support substrate. A peripheral edge portion of the resin insulation material exposed as a result of removal of a peripheral edge portion of the foil is adhered to the foil of the support substrate. A plurality of conductor layers and a plurality of resin insulation layers are laminated so as to obtain a laminate structure having a wiring laminate portion, which is to become the multilayer wiring substrate. The laminate structure is cut along a boundary between the wiring laminate portion and a surrounding portion, and the surrounding portion is removed. The wiring laminate portion is separated from the support substrate along the boundary between the two foils.

Abstract translation: 提供一种制造多层布线基板的方法。 使金属箔包覆的树脂绝缘材料的箔与覆盖金属箔的支撑衬底的箔接触。 由于去除箔的周缘部而露出的树脂绝缘材料的周边部分被粘附到支撑基板的箔上。 层叠多个导体层和多个树脂绝缘层，以获得具有将成为多层布线基板的布线层叠部分的层叠结构。 层叠结构沿着布线层压体部分和周围部分之间的边界被切割，并且周围部分被去除。 布线层叠部分沿着两个箔片之间的边界与支撑基板分离。

公开(公告)号：US08772643B2

公开(公告)日：2014-07-08

申请号：US13028545

申请日：2011-02-16

Applicant: Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

Inventor： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

IPC: H05K1/09

CPC classification number: H05K3/4682 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0588 ,  Y10T29/302 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract translation: 在布线层叠部的顶面侧的树脂绝缘层上形成有多个开口部，在其底面侧的树脂绝缘层上形成有多个开口部。 多个连接端子被设置成对应于这些开口。 连接端子的端子外表面的外围部分被顶表面侧上的树脂绝缘层覆盖，并且连接端子的端子外表面的周边部分被底表面侧上的树脂绝缘层覆盖。 每个第二主表面侧连接端子在端子外表面的中心具有凹部，并且凹部的最深部相对于端子外表面的周边部位于内侧 。

公开(公告)号：US08723328B2

公开(公告)日：2014-05-13

申请号：US13324535

申请日：2011-12-13

Applicant: Shinnosuke Maeda

Inventor： Shinnosuke Maeda

IPC: H01L23/522 ,  H01L23/498

Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.

公开(公告)号：US08609995B2

公开(公告)日：2013-12-17

申请号：US13184661

申请日：2011-07-18

Applicant: Shinnosuke Maeda ,  Satoshi Hirano ,  Yuuki Shiiba

Inventor： Shinnosuke Maeda ,  Satoshi Hirano ,  Yuuki Shiiba

IPC: H05K1/00

CPC classification number: H05K3/0035 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0373 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/09827 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Disclosed is a manufacturing method of a multilayer wiring board. The multilayer wiring board includes an outer resin insulation layer made of an insulating resin material, containing a filler of inorganic oxide and having an outer surface defining a chip mounting area to which an electronic chip is mounted with an underfill material filled in between the outer resin insulation layer and the electronic chip and holes through which conductor parts are exposed. The manufacturing method includes a hole forming step of forming the holes in the outer resin insulation layer by laser processing, a desmear treatment step of, after the hole forming step, removing smears from inside the holes of the outer resin insulation layer, and a filler reducing step of, after the desmear treatment step, reducing the amount of the filler exposed at the outer surface of the outer resin insulation layer.

Abstract translation: 公开了一种多层布线板的制造方法。 多层布线基板包括由绝缘树脂材料制成的外部树脂绝缘层，其包含无机氧化物的填料，并且具有限定芯片安装区域的外表面，电子芯片安装有填充在外部树脂之间的底部填充材料 绝缘层以及导体部件露出的电子芯片和孔。 该制造方法包括：通过激光加工在外树脂绝缘层中形成孔的孔形成步骤，在孔形成步骤之后的去污处理步骤，从外树脂绝缘层的孔内部除去污迹，以及填料 在去污处理步骤之后，减少在外树脂绝缘层的外表面暴露的填料的量。

公开(公告)号：US08129828B2

公开(公告)日：2012-03-06

申请号：US12568185

申请日：2009-09-28

Applicant: Shinnosuke Maeda

Inventor： Shinnosuke Maeda

IPC: H01L23/02

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate assembly includes a resin wiring substrate and a reinforcement member. The resin wiring substrate does not have a core substrate, and includes a substrate main surface, a substrate back surface, a laminate structure comprised of resin insulation layers and conductive layers, and connection terminals disposed on the substrate main surface, to which a chip component is connectable. The reinforcement member is bonded to the substrate main surface and defines an opening portion extending through the reinforcement member so as to expose the main-surface-side connection terminals. The reinforcement member comprises a composite material including a resin material containing an inorganic material.

Abstract translation: 布线基板组件包括树脂布线基板和加强件。 树脂布线基板不具有芯基板，并且包括基板主表面，基板背面，由树脂绝缘层和导电层构成的层叠结构，以及设置在基板主表面上的连接端子，芯片部件 是可连接的 加强构件结合到基板主表面并且限定延伸穿过加强构件的开口部，以暴露主表面侧连接端子。 加强构件包括包含含有无机材料的树脂材料的复合材料。

公开(公告)号：US20120024582A1

公开(公告)日：2012-02-02

申请号：US13195290

申请日：2011-08-01

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO

IPC: H05K1/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4015 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/10977 ,  H05K2201/2009 ,  H05K2203/041 ,  H01L2924/00

Abstract: A multilayer wiring substrate includes a laminate structure in which resin insulation layers and conductor layers are alternately laminated. The resin insulation layers include first-type resin insulation layers, and second-type resin insulation layers, each of which contains an inorganic material in a larger amount and is smaller in thermal expansion coefficient as compared with first-type resin insulation layers. On a cross section of the laminate structure taken along a thickness direction thereof, the ratio of a total thickness of the second-type resin insulation layers located in an area A2 to a thickness corresponding to the area A2 is greater than the ratio of a total thickness of the second-type resin insulation layers located in an area A1 to a thickness corresponding to the area A1. The laminate structure is warped such that the laminate structure is convex toward the side where the second main face is present.

Abstract translation: 多层布线基板包括层叠结构，其中树脂绝缘层和导体层交替层叠。 树脂绝缘层包括第一类树脂绝缘层和第二类树脂绝缘层，其中第二类树脂绝缘层与第一类型树脂绝缘层相比，其中含有大量的无机材料并且热膨胀系数较小。 在沿其厚度方向截取的层叠结构的横截面上，位于A2区域中的第二类树脂绝缘层的总厚度与对应于区域A2的厚度的比率大于总共 位于区域A1中的第二类型树脂绝缘层的厚度为对应于区域A1的厚度。 层压结构翘曲，使得层压结构向第二主面存在的一侧凸出。

公开(公告)号：US20110284269A1

公开(公告)日：2011-11-24

申请号：US13109521

申请日：2011-05-17

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO

IPC: H05K1/09

CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09472

Abstract: To provide a multilayer wiring substrate which can prevent migration of copper between wiring traces to thereby realize a higher degree of integration, a solder resist layer 25 having a plurality of openings 35, 36 is disposed on a top surface 31 side, and IC-chip connection terminals 41 and capacitor connection terminals 42 are buried in an outermost resin insulation layer 23 in contact with the solder resist layer 25. Each of the IC-chip connection terminals 41 and the capacitor connection terminals 42 is composed of a copper layer 44 and a plating layer 46 covering the outer surface of the copper layer 44. A conductor layer 26 present at the interface between the solder resist layer 25 and the resin insulation layer 23 is composed of a copper layer 27 and a nickel plating layer 28 covering the outer surface of the copper layer 27.

Abstract translation: 为了提供能够防止布线迹线之间的铜迁移从而实现更高的集成度的多层布线基板，具有多个开口部35,36的阻焊层25设置在顶面31侧，IC芯片 连接端子41和电容器连接端子42埋在与阻焊层25接触的最外层树脂绝缘层23中。每个IC芯片连接端子41和电容器连接端子42由铜层44和 镀覆层46覆盖铜层44的外表面。存在于阻焊层25和树脂绝缘层23之间的界面处的导体层26由铜层27和覆盖外表面的镀镍层28构成 的铜层27。

公开(公告)号：US20110211320A1

公开(公告)日：2011-09-01

申请号：US13031735

申请日：2011-02-22

Applicant: Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Takuya TORII ,  Tetsuo SUZUKI ,  Satoshi HIRANO

IPC: H05K7/00 ,  H05K3/36

CPC classification number: H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/4682 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

Abstract translation: 多层布线基板包括布置在堆叠构造的第一主表面上的第一主表面侧连接端子; 其中，所述第一主面侧连接端子包括IC芯片连接端子和无源元件连接端子; IC芯片连接端子位于形成在最外层的树脂绝缘层中的开口中; 无源元件连接端子由形成在树脂绝缘层上的上端子部和位于树脂绝缘层中的上端子部的内侧的开口部的下端子部构成， 并且其中所述上端子部分的上表面高于参考表面，并且所述IC芯片连接端子和所述下端子部分的上表面的高度与所述基准表面的高度相同或更低。

公开(公告)号：US20110198114A1

公开(公告)日：2011-08-18

申请号：US13028545

申请日：2011-02-16

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

IPC: H05K1/09 ,  H01R43/00 ,  H05K1/00

CPC classification number: H05K3/4682 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0588 ,  Y10T29/302 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract translation: 在布线层叠部的顶面侧的树脂绝缘层上形成有多个开口部，在其底面侧的树脂绝缘层上形成有多个开口部。 多个连接端子被设置成对应于这些开口。 连接端子的端子外表面的外围部分被顶表面侧上的树脂绝缘层覆盖，并且连接端子的端子外表面的周边部分被底表面侧上的树脂绝缘层覆盖。 每个第二主表面侧连接端子在端子外表面的中心具有凹部，并且凹部的最深部相对于端子外表面的周边部位于内侧 。

公开(公告)号：US20110155438A1

公开(公告)日：2011-06-30

申请号：US12978750

申请日：2010-12-27

Applicant: Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

Inventor： Tatsuya ITO ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Shinnosuke MAEDA ,  Atsuhiko SUGIMOTO ,  Satoshi HIRANO

IPC: H05K1/11

CPC classification number: H05K3/4682 ,  H05K1/113 ,  H05K3/4007 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/09472

Abstract: A multilayer wiring substrate has a multilayer wiring laminate portion in which a plurality of resin insulation layers made primarily of the same resin insulation material, and a plurality of conductive layers are laminated alternately. A plurality of first-main-surface-side connection terminals are disposed on one side of the laminate structure where a first main surface thereof is present, and a plurality of second-main-surface-side connection terminals being disposed on an other side of the laminate structure where a second main surface thereof is present. The plurality of conductive layers are formed in the plurality of resin insulation layers and interconnected by means of via conductors whose diameters increase toward the first main surface or the second main surface. The plurality of first-main-surface-side connection terminals comprising at least two types of terminals for connection of different articles-to-be-connected. Top surfaces of the plurality of first-main-surface-side connection terminals differ in height according to types of the articles-to-be-connected.

Abstract translation: 多层布线基板具有多层布线层叠部，其中主要由相同树脂绝缘材料制成的多个树脂绝缘层和多个导电层交替层叠。 多个第一主表面侧连接端子设置在层叠结构的存在第一主表面的一侧上，并且多个第二主表面侧连接端子设置在 其中存在第二主表面的层压结构。 多个导电层形成在多个树脂绝缘层中，并且通过直径朝向第一主表面或第二主表面增大的通孔导体互连。 多个第一主表面侧连接端子包括用于连接不同待连接物品的至少两种类型的端子。 多个第一主表面侧连接端子的顶表面根据要连接的物品的类型而不同。